main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers 93lc46bt-e: viewers · Ray 3d ago
93lc46bt-e-etched.glb Publish 0.1.0 · Ray 3d ago
93lc46bt-e-etched.step 93lc46bt-e: factory component page (tier=mfr) · Ray 3d ago
93lc46bt-e-hero.glb 93lc46bt-e: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
93lc46bt-e-hero.overlay.json Publish 0.1.0 · Ray 3d ago
93lc46bt-e.glb Publish 0.1.0 · Ray 3d ago
93lc46bt-e.kicad_mod Publish 0.1.0 · Ray 3d ago
93lc46bt-e.kicad_sym Publish 0.1.0 · Ray 3d ago
93lc46bt-e.lbr Publish 0.1.0 · Ray 3d ago
93lc46bt-e.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago

93LC46BT-E

Microchip Tech · EEPROM · SOT-23-6

93LC46BT-E from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DO output Data Out drives read data synchronously with CLK (TPD after the positive CLK edge) and shows Ready/Busy status during erase/write, going High-Z if CS is held low through the cycle.
2 VSS power_in Ground reference for the device.
3 DI input Data In clocks in the Start bit, opcode, address and data synchronously with CLK.
4 CLK input Serial Data Clock; opcodes, address and data bits are clocked in on its positive edge, and CLK is a don't-care while CS is low.
5 CS input Chip Select: high selects the device, low deselects it and forces Standby mode, and CS must be low for 250 ns minimum (TCSL) between consecutive instructions.
6 VCC power_in Power supply; the 93LC46B is specified for VCC of 2.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOT-23-6
Category Memory
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VCC) absolute maximum VCC 7 V 3
Voltage on all inputs and outputs w.r.t. VSS (minimum) -0.6 V 3
Storage temperature -65 150 °C 3
Ambient temperature with power applied -40 125 °C 3
ESD protection on all pins 4 kV 3
Supply voltage VCC (Automotive E grade) VCC 2.5 5.5 V Automotive (E), TA = -40°C to +125°C 3
Ambient temperature range (Automotive E grade) TA -40 125 °C Automotive (E), VCC = 2.5V to 5.5V 3
High-level input voltage VIH1 VIH1 2 V VCC 2.7V 3
Low-level input voltage VIL1 VIL1 -0.3 0.8 V VCC 2.7V 3
Low-level output voltage VOL1 VOL1 0.4 V IOL = 2.1 mA, VCC = 4.5V 3
Low-level output voltage VOL2 VOL2 0.2 V IOL = 100 µA, VCC = 2.5V 3
High-level output voltage VOH1 VOH1 2.4 V IOH = -400 µA, VCC = 4.5V 3
Input leakage current ILI -1 1 µA VIN = VSS or VCC 3
Output leakage current ILO -1 1 µA VOUT = VSS or VCC 3
Pin capacitance (all inputs/outputs) CIN, COUT 7 pF VIN/VOUT = 0V (Note 1); TA = 25°C, FCLK = 1 MHz 3
Standby current (E-Temp) ICCS 5 µA E-Temp; CLK = CS = 0V; ORG = DI = VSS or VCC (Note 2) (Note 3) 3
Clock frequency FCLK 2 MHz 2.5V ≤ VCC ≤ 5.5V 4
Clock high time TCKH 250 ns 2.5V ≤ VCC ≤ 5.5V 4
Clock low time TCKL 200 ns 2.5V ≤ VCC ≤ 5.5V 4
Chip select setup time TCSS 50 ns 4.5V ≤ VCC ≤ 5.5V 4
Chip select setup time TCSS 100 ns 2.5V ≤ VCC ≤ 4.5V 4
Chip select hold time TCSH 0 ns 1.8V ≤ VCC ≤ 5.5V 4
Chip select low time TCSL 250 ns 1.8V ≤ VCC ≤ 5.5V 4
Data input setup time TDIS 100 ns 2.5V ≤ VCC ≤ 5.5V 4
Data input hold time TDIH 100 ns 2.5V ≤ VCC ≤ 5.5V 4
Data output delay time TPD 200 ns 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF 4
Data output delay time TPD 250 ns 2.5V ≤ VCC ≤ 4.5V, CL = 100 pF 4
Data output disable time TCZ 100 ns 4.5V ≤ VCC ≤ 5.5V, (Note 1) 4
Data output disable time TCZ 200 ns 1.8V ≤ VCC ≤ 4.5V, (Note 1) 4
Status valid time TSV 200 ns 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF 4
Status valid time TSV 300 ns 2.5V ≤ VCC ≤ 4.5V, CL = 100 pF 4
Program cycle time (erase/write) TWC 6 ms Erase/Write mode (AA and LC versions) 4
ERAL cycle time TEC 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V 4
WRAL cycle time TWL 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 2x3 DFN/TDFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish. 1

CAD (KiCad official)

  • Symbol: 93LC46BT-E
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: 93lc46bt-e-etched.step / 93lc46bt-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 93lc46bt-e.step / 93lc46bt-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (38 pp, sha256 847c062ab2841168, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF