component

93LC46B-I

Public Made by Adom

by adom

Microchip Tech EEPROM, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemory93lc46b-ifactory-2.0.0extractor-text

Verified 93LC46B-I

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 93LC46B-I · DIP-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 38-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: DIP-8_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-c31bzoyz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 93lc46b-i.kicad_sym✓ 93lc46b-i.kicad_mod✓ 93lc46b-i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 21h ago
viewers 93lc46b-i: viewers · Ray 21h ago
93lc46b-i-etched.glb Publish 0.1.0 · Ray 21h ago
93lc46b-i-etched.step 93lc46b-i: factory component page (tier=mfr) · Ray 21h ago
93lc46b-i-hero.glb 93lc46b-i: hero GLB from the etched model (keeps the MPN mark) · Ray 21h ago
93lc46b-i-hero.overlay.json Publish 0.1.0 · Ray 21h ago
93lc46b-i.glb Publish 0.1.0 · Ray 21h ago
93lc46b-i.kicad_mod Publish 0.1.0 · Ray 21h ago
93lc46b-i.kicad_sym Publish 0.1.0 · Ray 21h ago
93lc46b-i.lbr Publish 0.1.0 · Ray 21h ago
93lc46b-i.step Publish 0.1.0 · Ray 21h ago
package.json Publish 0.1.0 · Ray 21h ago
page.json Set visibility: public · Ray 21h ago
README.md Publish 0.1.0 · Ray 21h ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 21h ago

93LC46B-I

Microchip Tech · EEPROM · DIP-8

93LC46B-I from Microchip Tech, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input A high level selects the device and a low level deselects it and forces it into Standby mode, with CS low for 250 ns minimum (TCSL) between consecutive instructions.
2 CLK input The Serial Clock synchronizes communication, with opcodes, address and data bits clocked in and data bits clocked out on the positive edge of CLK.
3 DI input Data In clocks in a Start bit, opcode, address and data synchronously with the CLK input.
4 DO output Data Out outputs data synchronously with CLK in Read mode (TPD after the positive edge of CLK) and provides Ready/Busy status during erase and write cycles when CS is brought high after TCSL.
5 VSS power_in Ground reference for the device.
6 ORG/NC unconnected On 93XX46A/B devices this pin is No Internal Connection (ORG is only used on the 93XX46C), so for the 93LC46B it has no internal connection and must not be relied on as an ORG input.
7 NC unconnected No Internal Connection.
8 VCC power_in Power supply; the 93LC46B operates from 2.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package DIP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level input voltage VIH1 2 V VCC 2.7V 3
Low-level input voltage VIL1 -0.3 0.8 V VCC 2.7V 3
Low-level input voltage VIL2 -0.3 V VCC 2.7V 3
Low-level output voltage VOL1 0.4 V IOL = 2.1 mA, VCC = 4.5V 3
Low-level output voltage VOL2 0.2 V IOL = 100 µA, VCC = 2.5V 3
High-level output voltage VOH1 2.4 V IOH = -400 µA, VCC = 4.5V 3
Input leakage current ILI -1 1 µA VIN = VSS or VCC 3
Output leakage current ILO -1 1 µA VOUT = VSS or VCC 3
Pin capacitance (all inputs/outputs) CIN, COUT 7 pF VIN/VOUT = 0V (Note 1); TA = 25°C, FCLK = 1 MHz 3
Standby current ICCS 1 µA I-Temp; CLK = CS = 0V; ORG = DI = VSS or VCC (Notes 2, 3) 3
Clock frequency FCLK 2 MHz 2.5V ≤ VCC ≤ 5.5V 4
Clock high time TCKH 250 ns 2.5V ≤ VCC ≤ 5.5V 4
Clock low time TCKL 200 ns 2.5V ≤ VCC ≤ 5.5V 4
Chip Select setup time TCSS 100 ns 2.5V ≤ VCC ≤ 4.5V 4
Chip Select setup time TCSS 50 ns 4.5V ≤ VCC ≤ 5.5V 4
Chip Select hold time TCSH 0 ns 1.8V ≤ VCC ≤ 5.5V 4
Chip Select low time TCSL 250 ns 1.8V ≤ VCC ≤ 5.5V 4
Data input setup time TDIS 100 ns 2.5V ≤ VCC ≤ 5.5V 4
Data input hold time TDIH 100 ns 2.5V ≤ VCC ≤ 5.5V 4
Data output delay time TPD 200 ns 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF 4
Data output delay time TPD 250 ns 2.5V ≤ VCC ≤ 4.5V, CL = 100 pF 4
Data output disable time TCZ 100 ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 4
Data output disable time TCZ 200 ns 1.8V ≤ VCC ≤ 4.5V (Note 1) 4
Status valid time TSV 200 ns 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF 4
Status valid time TSV 300 ns 2.5V ≤ VCC ≤ 4.5V, CL = 100 pF 4
Program cycle time TWC 6 ms Erase/Write mode (AA and LC versions) 4
Erase all cycle time TEC 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V 4
Write all cycle time TWL 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V 4
Supply voltage (VCC) absolute maximum VCC 7 V 3
All inputs and outputs w.r.t. VSS -0.6 V w.r.t. VSS; upper limit printed as VCC + 1.0V 3
Storage temperature -65 150 °C 3
Ambient temperature with power applied -40 125 °C 3
Supply voltage range VCC 2.5 5.5 V 93LC46B device selection table 1
Industrial ambient temperature range TA -40 85 °C Industrial (I) grade (suffix -I) 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 2x3 DFN/TDFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish. 1

CAD (KiCad official)

  • Symbol: 93LC46B-I
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: DIP-8 (KiCad packages3D, STEP)
  • 3D model files: 93lc46b-i-etched.step / 93lc46b-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 93lc46b-i.step / 93lc46b-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (38 pp, sha256 bf6ca0ca8d588071, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF