component
93LC46A-I
Public Made by Adomby adom
Microchip Tech EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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93LC46A-I
Microchip Tech · EEPROM · SOIC-8
93LC46A-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select: a high level selects the device, a low level deselects it and forces Standby mode, and CS must be low for 250 ns minimum (TCSL) between consecutive instructions. |
| 2 | CLK | input | Serial Clock that synchronizes communication with the master; opcodes, address and data bits are clocked in (and data clocked out) on the positive edge of CLK. |
| 3 | DI | input | Serial Data In, used to clock in the Start bit, opcode, address and data synchronously with the CLK input. |
| 4 | DO | tri_state | Serial Data Out, which outputs read data synchronously with CLK (TPD after the positive edge) and gives Ready/Busy status during erase/write cycles; High-Z when CS is held low during the cycle. |
| 5 | VSS | power_in | Ground. |
| 6 | NC | unconnected | Listed as ORG/NC; the ORG pin is NC on 93LC46A devices, which are always x8 organization, so this pin has no internal connection. |
| 7 | NC | unconnected | No internal connection. |
| 8 | VCC | power_in | Power supply, 2.5 V to 5.5 V for the 93LC46A (VCC must be 4.5 V for proper operation of WRAL). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Low-level input voltage 1 | VIL1 | -0.3 | 0.8 | V | VCC ≥ 2.7V | 3 | |
| High-level input voltage 1 | VIH1 | 2 | V | VCC ≥ 2.7V | 3 | ||
| Low-level output voltage 1 | VOL1 | 0.4 | V | IOL = 2.1 mA, VCC = 4.5V | 3 | ||
| Low-level output voltage 2 | VOL2 | 0.2 | V | IOL = 100 µA, VCC = 2.5V | 3 | ||
| High-level output voltage 1 | VOH1 | 2.4 | V | IOH = -400 µA, VCC = 4.5V | 3 | ||
| Input leakage current | ILI | -1 | 1 | µA | VIN = VSS or VCC | 3 | |
| Output leakage current | ILO | -1 | 1 | µA | VOUT = VSS or VCC | 3 | |
| Pin capacitance (all inputs/outputs) | CIN, COUT | 7 | pF | VIN/VOUT = 0V (Note 1), TA = 25°C, FCLK = 1 MHz | 3 | ||
| Standby current, I-Temp | ICCS | 1 | µA | I-Temp, CLK = CS = 0V, ORG = DI = VSS or VCC | 3 | ||
| Clock frequency | FCLK | 2 | MHz | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Clock high time | TCKH | 250 | ns | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Clock low time | TCKL | 200 | ns | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Chip Select setup time | TCSS | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| Chip Select setup time | TCSS | 100 | ns | 2.5V ≤ VCC < 4.5V | 4 | ||
| Chip Select hold time | TCSH | 0 | ns | 1.8V ≤ VCC ≤ 5.5V | 4 | ||
| Chip Select low time | TCSL | 250 | ns | 1.8V ≤ VCC ≤ 5.5V | 4 | ||
| Data input setup time | TDIS | 100 | ns | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Data input hold time | TDIH | 100 | ns | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Data output delay time | TPD | 200 | ns | 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF | 4 | ||
| Data output delay time | TPD | 250 | ns | 2.5V ≤ VCC < 4.5V, CL = 100 pF | 4 | ||
| Data output disable time | TCZ | 100 | ns | 4.5V ≤ VCC ≤ 5.5V, (Note 1) | 4 | ||
| Data output disable time | TCZ | 200 | ns | 1.8V ≤ VCC < 4.5V, (Note 1) | 4 | ||
| Status valid time | TSV | 200 | ns | 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF | 4 | ||
| Status valid time | TSV | 300 | ns | 2.5V ≤ VCC < 4.5V, CL = 100 pF | 4 | ||
| Program cycle time | TWC | 6 | ms | Erase/Write mode (AA and LC versions) | 4 | ||
| ERAL cycle time | TEC | 6 | ms | ERAL mode, 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| WRAL cycle time | TWL | 15 | ms | WRAL mode, 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| VCC voltage detect | VPOR | 1.5 | V | (Note 1), 93AA46A/B/C, 93LC46A/B/C | 3 | ||
| Supply voltage VCC | VCC | 2.5 | 5.5 | V | 93LC46A | 1 | |
| Operating temperature, Industrial | TA | -40 | 85 | °C | Industrial (I) | 1 | |
| Supply voltage | VCC | 7 | V | 3 | |||
| All inputs and outputs w.r.t. VSS | -0.6 | V | -0.6V to VCC +1.0V | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| ESD protection on all pins | 4 | kV | printed as ≥ 4 kV (symbol lost in extraction) | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 2x3 DFN/TDFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish. | 1 |
CAD (KiCad official)
- Symbol:
93LC46A-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
93lc46a-i-etched.step/93lc46a-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);93lc46a-i.step/93lc46a-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (38 pp, sha256
96937bef2b6c48eb, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 93LC46A-I
**Microchip Tech** · EEPROM · SOIC-8
93LC46A-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select: a high level selects the device, a low level deselects it and forces Standby mode, and CS must be low for 250 ns minimum (TCSL) between consecutive instructions. |
| 2 | CLK | input | Serial Clock that synchronizes communication with the master; opcodes, address and data bits are clocked in (and data clocked out) on the positive edge of CLK. |
| 3 | DI | input | Serial Data In, used to clock in the Start bit, opcode, address and data synchronously with the CLK input. |
| 4 | DO | tri_state | Serial Data Out, which outputs read data synchronously with CLK (TPD after the positive edge) and gives Ready/Busy status during erase/write cycles; High-Z when CS is held low during the cycle. |
| 5 | VSS | power_in | Ground. |
| 6 | NC | unconnected | Listed as ORG/NC; the ORG pin is NC on 93LC46A devices, which are always x8 organization, so this pin has no internal connection. |
| 7 | NC | unconnected | No internal connection. |
| 8 | VCC | power_in | Power supply, 2.5 V to 5.5 V for the 93LC46A (VCC must be 4.5 V for proper operation of WRAL). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Low-level input voltage 1 | VIL1 | -0.3 | | 0.8 | V | VCC ≥ 2.7V | 3 |
| High-level input voltage 1 | VIH1 | 2 | | | V | VCC ≥ 2.7V | 3 |
| Low-level output voltage 1 | VOL1 | | | 0.4 | V | IOL = 2.1 mA, VCC = 4.5V | 3 |
| Low-level output voltage 2 | VOL2 | | | 0.2 | V | IOL = 100 µA, VCC = 2.5V | 3 |
| High-level output voltage 1 | VOH1 | 2.4 | | | V | IOH = -400 µA, VCC = 4.5V | 3 |
| Input leakage current | ILI | -1 | | 1 | µA | VIN = VSS or VCC | 3 |
| Output leakage current | ILO | -1 | | 1 | µA | VOUT = VSS or VCC | 3 |
| Pin capacitance (all inputs/outputs) | CIN, COUT | | | 7 | pF | VIN/VOUT = 0V (Note 1), TA = 25°C, FCLK = 1 MHz | 3 |
| Standby current, I-Temp | ICCS | | | 1 | µA | I-Temp, CLK = CS = 0V, ORG = DI = VSS or VCC | 3 |
| Clock frequency | FCLK | | | 2 | MHz | 2.5V ≤ VCC ≤ 5.5V | 4 |
| Clock high time | TCKH | 250 | | | ns | 2.5V ≤ VCC ≤ 5.5V | 4 |
| Clock low time | TCKL | 200 | | | ns | 2.5V ≤ VCC ≤ 5.5V | 4 |
| Chip Select setup time | TCSS | 50 | | | ns | 4.5V ≤ VCC ≤ 5.5V | 4 |
| Chip Select setup time | TCSS | 100 | | | ns | 2.5V ≤ VCC < 4.5V | 4 |
| Chip Select hold time | TCSH | 0 | | | ns | 1.8V ≤ VCC ≤ 5.5V | 4 |
| Chip Select low time | TCSL | 250 | | | ns | 1.8V ≤ VCC ≤ 5.5V | 4 |
| Data input setup time | TDIS | 100 | | | ns | 2.5V ≤ VCC ≤ 5.5V | 4 |
| Data input hold time | TDIH | 100 | | | ns | 2.5V ≤ VCC ≤ 5.5V | 4 |
| Data output delay time | TPD | | | 200 | ns | 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF | 4 |
| Data output delay time | TPD | | | 250 | ns | 2.5V ≤ VCC < 4.5V, CL = 100 pF | 4 |
| Data output disable time | TCZ | | | 100 | ns | 4.5V ≤ VCC ≤ 5.5V, (Note 1) | 4 |
| Data output disable time | TCZ | | | 200 | ns | 1.8V ≤ VCC < 4.5V, (Note 1) | 4 |
| Status valid time | TSV | | | 200 | ns | 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF | 4 |
| Status valid time | TSV | | | 300 | ns | 2.5V ≤ VCC < 4.5V, CL = 100 pF | 4 |
| Program cycle time | TWC | | | 6 | ms | Erase/Write mode (AA and LC versions) | 4 |
| ERAL cycle time | TEC | | | 6 | ms | ERAL mode, 4.5V ≤ VCC ≤ 5.5V | 4 |
| WRAL cycle time | TWL | | | 15 | ms | WRAL mode, 4.5V ≤ VCC ≤ 5.5V | 4 |
| VCC voltage detect | VPOR | | 1.5 | | V | (Note 1), 93AA46A/B/C, 93LC46A/B/C | 3 |
| Supply voltage VCC | VCC | 2.5 | | 5.5 | V | 93LC46A | 1 |
| Operating temperature, Industrial | TA | -40 | | 85 | °C | Industrial (I) | 1 |
| Supply voltage | VCC | | | 7 | V | | 3 |
| All inputs and outputs w.r.t. VSS | | -0.6 | | | V | -0.6V to VCC +1.0V | 3 |
| Storage temperature | | -65 | | 150 | °C | | 3 |
| Ambient temperature with power applied | | -40 | | 125 | °C | | 3 |
| ESD protection on all pins | | 4 | | | kV | printed as ≥ 4 kV (symbol lost in extraction) | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | 2x3 DFN/TDFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish. | 1 |
## CAD (KiCad official)
- Symbol: `93LC46A-I`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `93lc46a-i-etched.step` / `93lc46a-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `93lc46a-i.step` / `93lc46a-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/93lc46a-i-datasheet.pdf) (38 pp, sha256 `96937bef2b6c48eb`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/93lc46a-i-datasheet.pdf)