component
93C46BT-I
Public Made by Adomby adom
Microchip Tech EEPROM, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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93C46BT-I
Microchip Tech · EEPROM · SOT-23-6
93C46BT-I from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DO | tri_state | Data Out outputs read data synchronously with CLK and provides Ready/Busy status during erase/write cycles; High-Z when CS is held low during the cycle. |
| 2 | VSS | power_in | Ground. |
| 3 | DI | input | Data In clocks in the Start bit, opcode, address and data synchronously with the CLK input. |
| 4 | CLK | input | Serial Clock synchronizes communication with the master; opcodes, address and data bits are clocked in on the positive edge of CLK. |
| 5 | CS | input | Chip Select: a high level selects the device, a low level deselects it into Standby mode, and CS must be low for 250 ns minimum (TCSL) between instructions. |
| 6 | VCC | power_in | Power supply; 93C46 devices operate at 4.5-5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Memory |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage | VIH1 | 2 | V | VCC ≥ 2.7V | 3 | ||
| Low-level input voltage | VIL1 | -0.3 | 0.8 | V | VCC ≥ 2.7V | 3 | |
| Low-level output voltage | VOL1 | 0.4 | V | IOL = 2.1 mA, VCC = 4.5V | 3 | ||
| High-level output voltage | VOH1 | 2.4 | V | IOH = -400 µA, VCC = 4.5V | 3 | ||
| Input leakage current | ILI | -1 | 1 | µA | VIN = VSS or VCC | 3 | |
| Output leakage current | ILO | -1 | 1 | µA | VOUT = VSS or VCC | 3 | |
| Pin capacitance (all inputs/outputs) | CIN, COUT | 7 | pF | VIN/VOUT = 0V (Note 1), TA = 25°C, FCLK = 1 MHz | 3 | ||
| Standby current | ICCS | 1 | µA | I-Temp, CLK = CS = 0V, ORG = DI = VSS or VCC | 3 | ||
| Clock frequency | FCLK | 2 | MHz | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Clock high time | TCKH | 250 | ns | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Clock low time | TCKL | 200 | ns | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Chip Select setup time | TCSS | 50 | ns | 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| Chip Select hold time | TCSH | 0 | ns | 1.8V ≤ VCC ≤ 5.5V | 4 | ||
| Chip Select low time | TCSL | 250 | ns | 1.8V ≤ VCC ≤ 5.5V | 4 | ||
| Data input setup time | TDIS | 100 | ns | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Data input hold time | TDIH | 100 | ns | 2.5V ≤ VCC ≤ 5.5V | 4 | ||
| Data output delay time | TPD | 200 | ns | 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF | 4 | ||
| Data output disable time | TCZ | 100 | ns | 4.5V ≤ VCC ≤ 5.5V, (Note 1) | 4 | ||
| Status valid time | TSV | 200 | ns | 4.5V ≤ VCC ≤ 5.5V, CL = 100 pF | 4 | ||
| Program cycle time | TWC | 2 | ms | Erase/Write mode (93C versions) | 4 | ||
| Program cycle time (ERAL) | TEC | 6 | ms | ERAL mode, 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| Program cycle time (WRAL) | TWL | 15 | ms | WRAL mode, 4.5V ≤ VCC ≤ 5.5V | 4 | ||
| VCC voltage detect | VPOR | 3.8 | V | 93C46A/B/C (Note 1) | 3 | ||
| Supply voltage VCC range | VCC | 4.5 | 5.5 | V | 93C46B | 1 | |
| Operating ambient temperature (Industrial) | TA | -40 | 85 | °C | Industrial (I) | 3 | |
| Supply voltage | VCC | 7 | V | 3 | |||
| All inputs and outputs w.r.t. VSS | -0.6 | V | -0.6V to VCC +1.0V | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| ESD protection on all pins | 4 | kV | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 2x3 DFN/TDFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish. | 1 |
CAD (KiCad official)
- Symbol:
93C46BT-I - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
93c46bt-i-etched.step/93c46bt-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);93c46bt-i.step/93c46bt-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (38 pp, sha256
56765a2c944815f8, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).