component
93AA66A-I
Public Made by Adomby adom
Microchip Tech Pre-ordered Chips, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 10d ago |
| viewers | 10d ago |
| 93aa66a-i-etched.glb | 10d ago |
| 93aa66a-i-etched.step | 10d ago |
| 93aa66a-i-hero.glb | 10d ago |
| 93aa66a-i-hero.overlay.json | 10d ago |
| 93aa66a-i.glb | 10d ago |
| 93aa66a-i.kicad_mod | 10d ago |
| 93aa66a-i.kicad_sym | 10d ago |
| 93aa66a-i.lbr | 10d ago |
| 93aa66a-i.step | 10d ago |
| package.json | 10d ago |
| page.json | 10d ago |
| README.md | 10d ago |
93AA66A-I
Microchip Tech · Pre-ordered Chips · MSOP-8
93AA66A-I from Microchip Tech, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select: a high level selects the device, a low level deselects it and forces Standby mode, and CS must be low for 250 ns minimum (TCSL) between consecutive instructions. |
| 2 | CLK | input | Serial Clock that synchronizes host communication, with opcode, address and data bits clocked in (and data clocked out) on the positive edge of CLK. |
| 3 | DI | input | Data In, used to clock in the Start bit, opcode, address and data synchronously with the CLK input. |
| 4 | DO | tri_state | Data Out, outputs data in Read mode synchronously with CLK and provides Ready/Busy status during erase and write cycles; High-Z when CS is held low during the cycle. |
| 5 | VSS | power_in | Ground. |
| 6 | NC | unconnected | ORG/NC pin: ORG on 93XX66C devices, but no internal connection on 93XX66A/B devices (this 93AA66A is x8 only). |
| 7 | NC | unconnected | No internal connection. |
| 8 | VCC | power_in | Power supply; 1.8V to 5.5V for the 93AA66A, and VCC must be 4.5V or higher for proper operation of WRAL. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 7 | V | 3 | |||
| All inputs and outputs w.r.t. VSS | -0.6 | V | -0.6V to VCC +1.0V | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 3 | |||
| ESD protection on all pins | 4 | kV | ≥ 4 kV | 3 | |||
| Supply voltage range (Industrial) | VCC | 1.8 | 5.5 | V | Industrial (I) | 3 | |
| Operating temperature (Industrial) | TA | -40 | 85 | °C | Industrial (I) | 3 | |
| High-level input voltage 1 | VIH1 | 2 | V | VCC ≥ 2.7V; max printed as VCC +1 | 3 | ||
| High-level input voltage 2 | VIH2 | 0.7 | xVCC | VCC < 2.7V; min printed as 0.7 VCC, max VCC +1 | 3 | ||
| Low-level input voltage 1 | VIL1 | -0.3 | 0.8 | V | VCC ≥ 2.7V | 3 | |
| Low-level input voltage 2 | VIL2 | -0.3 | V | VCC < 2.7V; max printed as 0.2 VCC | 3 | ||
| Low-level output voltage 1 | VOL1 | 0.4 | V | IOL = 2.1 mA, VCC = 4.5V | 3 | ||
| Low-level output voltage 2 | VOL2 | 0.2 | V | IOL = 100 µA, VCC = 2.5V | 3 | ||
| High-level output voltage 1 | VOH1 | 2.4 | V | IOH = -400 µA, VCC = 4.5V | 3 | ||
| Input leakage current | ILI | -1 | 1 | µA | VIN = VSS or VCC | 3 | |
| Output leakage current | ILO | -1 | 1 | µA | VOUT = VSS or VCC | 3 | |
| Pin capacitance (all inputs/outputs) | CIN, COUT | 7 | pF | VIN/VOUT = 0V, TA = +25°C, FCLK = 1 MHz (Note 1) | 3 | ||
| Write current | ICC write | 2 | mA | FCLK = 3 MHz, Vcc = 5.5V | 3 | ||
| Read current | ICC read | 1 | mA | FCLK = 3 MHz, VCC = 5.5V | 3 | ||
| Read current | ICC read | 500 | µA | FCLK = 2 MHz, VCC = 3.0V | 3 | ||
| Standby current (I-Temp) | ICCS | 1 | µA | CS = 0V, ORG = DI = CLK = VSS or VCC | 3 | ||
| Clock frequency | FCLK | 2 | MHz | 2.5V ≤ VCC < 5.5V | 4 | ||
| Clock frequency | FCLK | 1 | MHz | 1.8V ≤ VCC < 2.5V | 4 | ||
| Clock high time | TCKH | 250 | ns | 2.5V ≤ VCC < 5.5V | 4 | ||
| Clock high time | TCKH | 450 | ns | 1.8V ≤ VCC < 2.5V | 4 | ||
| Clock low time | TCKL | 200 | ns | 2.5V ≤ VCC < 5.5V | 4 | ||
| Clock low time | TCKL | 450 | ns | 1.8V ≤ VCC < 2.5V | 4 | ||
| Chip select setup time | TCSS | 50 | ns | 4.5V ≤ VCC < 5.5V | 4 | ||
| Chip select setup time | TCSS | 100 | ns | 2.5V ≤ VCC < 4.5V | 4 | ||
| Chip select setup time | TCSS | 250 | ns | 1.8V ≤ VCC < 2.5V | 4 | ||
| Chip select hold time | TCSH | 0 | ns | 1.8V ≤ VCC < 5.5V | 4 | ||
| Chip select low time | TCSL | 250 | ns | 1.8V ≤ VCC < 5.5V | 4 | ||
| Data input setup time | TDIS | 100 | ns | 2.5V ≤ VCC < 5.5V | 4 | ||
| Data input setup time | TDIS | 250 | ns | 1.8V ≤ VCC < 2.5V | 4 | ||
| Data input hold time | TDIH | 100 | ns | 2.5V ≤ VCC < 5.5V | 4 | ||
| Data input hold time | TDIH | 250 | ns | 1.8V ≤ VCC < 2.5V | 4 | ||
| Data output delay time | TPD | 200 | ns | 4.5V ≤ VCC < 5.5V, CL = 100 pF | 4 | ||
| Data output delay time | TPD | 250 | ns | 2.5V ≤ VCC < 4.5V, CL = 100 pF | 4 | ||
| Data output delay time | TPD | 400 | ns | 1.8V ≤ VCC < 2.5V, CL = 100 pF | 4 | ||
| Data output disable time | TCZ | 100 | ns | 4.5V ≤ VCC < 5.5V, (Note 1) | 4 | ||
| Data output disable time | TCZ | 200 | ns | 1.8V ≤ VCC < 4.5V, (Note 1) | 4 | ||
| Status valid time | TSV | 200 | ns | 4.5V ≤ VCC < 5.5V, CL = 100 pF | 4 | ||
| Status valid time | TSV | 300 | ns | 2.5V ≤ VCC < 4.5V, CL = 100 pF | 4 | ||
| Status valid time | TSV | 500 | ns | 1.8V ≤ VCC < 2.5V, CL = 100 pF | 4 | ||
| Program cycle time | TWC | 6 | ms | Erase/Write mode (AA and LC versions) | 5 | ||
| ERAL cycle time | TEC | 6 | ms | ERAL mode, 4.5V ≤ VCC ≤ 5.5V | 5 | ||
| WRAL cycle time | TWL | 15 | ms | WRAL mode, 4.5V ≤ VCC ≤ 5.5V | 5 | ||
| Write current | ICC write | 500 | µA | FCLK = 2 MHz, Vcc = 2.5V | 3 | ||
| Read current | ICC read | 100 | µA | FCLK = 2 MHz, VCC = 2.5V | 3 | ||
| VCC voltage detect | VPOR | 1.5 | V | 93AA66A/B/C, 93LC66A/B/C (Note 1) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Part Number VCC Range ORG Pin Word Size Temperature Ranges Packages 93AA66A 1.8V-5.5V No 8-bit I MC, MS, P, SN, OT, MN,ST | 1 |
CAD (KiCad official)
- Symbol:
93AA66A-I - Footprint:
Package_SO:MSOP-8_3x3mm_P0.65mm - 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files:
93aa66a-i-etched.step/93aa66a-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);93aa66a-i.step/93aa66a-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (43 pp, sha256
04494d6624e9f111, retrieved 2026-10-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).