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93AA56CT-I

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by adom

Microchip Tech EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemory93aa56ct-ifactory-2.0.0extractor-text

Verified 93AA56CT-I

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 93AA56CT-I · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 42-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-a9opx4tt/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.26)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 93aa56ct-i.kicad_sym✓ 93aa56ct-i.kicad_mod✓ 93aa56ct-i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers 93aa56ct-i: viewers · Ray 3d ago
93aa56ct-i-etched.glb Publish 0.1.0 · Ray 3d ago
93aa56ct-i-etched.step 93aa56ct-i: factory component page (tier=mfr) · Ray 3d ago
93aa56ct-i-hero.glb 93aa56ct-i: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
93aa56ct-i-hero.overlay.json Publish 0.1.0 · Ray 3d ago
93aa56ct-i.glb Publish 0.1.0 · Ray 3d ago
93aa56ct-i.kicad_mod Publish 0.1.0 · Ray 3d ago
93aa56ct-i.kicad_sym Publish 0.1.0 · Ray 3d ago
93aa56ct-i.lbr Publish 0.1.0 · Ray 3d ago
93aa56ct-i.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 3d ago

93AA56CT-I

Microchip Tech · EEPROM · SOIC-8

93AA56CT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select: a high level selects the device, a low level deselects it and forces Standby mode, and CS must be low for at least 250 ns (TCSL) between consecutive instructions.
2 CLK input Serial Clock that synchronizes host communication; opcodes, address and data bits are clocked in (and data clocked out) on the positive edge of CLK.
3 DI input Serial Data In, used to clock in the Start bit, opcode, address and data synchronously with CLK.
4 DO tri_state Serial Data Out: outputs read data synchronously with CLK and provides Ready/Busy status during erase/write cycles, and is High-Z when CS is held low during the cycle.
5 VSS power_in Ground.
6 ORG input Memory configuration on the 93AA56C: tie to VCC or logic high for x16 organization, tie to VSS or logic low for x8, and it must be tied to a valid logic level.
7 NC unconnected No internal connection.
8 VCC power_in Power supply (1.8V to 5.5V for the 93AA56C).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (Industrial) VCC 1.8 5.5 V Industrial (I) 3
Operating temperature (Industrial) TA -40 85 °C Industrial (I) 3
Supply voltage VCC 7 V 3
All inputs and outputs w.r.t. VSS -0.6 V Max printed as VCC +1.0V 3
Storage temperature -65 150 °C 3
Ambient temperature with power applied -40 125 °C 3
ESD protection on all pins 4 kV 3
High-level input voltage 1 VIH1 2 V VCC ≥ 2.7V; max printed as VCC +1 3
Low-level input voltage 1 VIL1 -0.3 0.8 V VCC ≥ 2.7V 3
Low-level input voltage 2 VIL2 -0.3 V VCC < 2.7V; max printed as 0.2 VCC 3
Low-level output voltage 1 VOL1 0.4 V IOL = 2.1 mA, VCC = 4.5V 3
Low-level output voltage 2 VOL2 0.2 V IOL = 100 µA, VCC = 2.5V 3
High-level output voltage 1 VOH1 2.4 V IOH = -400 µA, VCC = 4.5V 3
Input leakage current ILI -1 1 µA VIN = VSS or VCC 3
Output leakage current ILO -1 1 µA VOUT = VSS or VCC 3
Pin capacitance (all inputs/outputs) CIN, COUT 7 pF VIN/VOUT = 0V, TA = +25°C, FCLK = 1 MHz 3
Write current ICC write 2 mA FCLK = 3 MHz, Vcc = 5.5V 3
Write current (typical) ICC write 500 µA FCLK = 2 MHz, Vcc = 2.5V 3
Read current ICC read 1 mA FCLK = 3 MHz, VCC = 5.5V 3
Read current ICC read 500 µA FCLK = 2 MHz, VCC = 3.0V 3
Read current (typical) ICC read 100 µA FCLK = 2 MHz, VCC = 2.5V 3
Standby current (I temp) ICCS 1 µA I, Temp, CLK = CS = 0V, ORG = DI = VSS or VCC 3
VCC voltage detect VPOR 1.5 V 93AA56A/B/C, 93LC56A/B/C (Note 1) 4
Clock frequency FCLK 3 MHz 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Clock frequency FCLK 2 MHz 2.5V ≤ VCC < 5.5V 4
Clock frequency FCLK 1 MHz 1.8V ≤ VCC < 2.5V 4
Clock high time TCKH 200 ns 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Clock high time TCKH 250 ns 2.5V ≤ VCC < 5.5V 4
Clock high time TCKH 450 ns 1.8V ≤ VCC < 2.5V 4
Clock low time TCKL 100 ns 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Clock low time TCKL 200 ns 2.5V ≤ VCC < 5.5V 4
Clock low time TCKL 450 ns 1.8V ≤ VCC < 2.5V 4
Chip Select setup time TCSS 50 ns 4.5V ≤ VCC < 5.5V 4
Chip Select setup time TCSS 100 ns 2.5V ≤ VCC < 4.5V 4
Chip Select setup time TCSS 250 ns 1.8V ≤ VCC < 2.5V 4
Chip Select hold time TCSH 0 ns 1.8V ≤ VCC < 5.5V 4
Chip Select low time TCSL 250 ns 1.8V ≤ VCC < 5.5V 4
Data input setup time TDIS 50 ns 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Data input setup time TDIS 100 ns 2.5V ≤ VCC < 5.5V 4
Data input setup time TDIS 250 ns 1.8V ≤ VCC < 2.5V 4
Data input hold time TDIH 50 ns 4.5V ≤ VCC < 5.5V, 93XX56C only 4
Data input hold time TDIH 100 ns 2.5V ≤ VCC < 5.5V 4
Data input hold time TDIH 250 ns 1.8V ≤ VCC < 2.5V 4
Data output delay time TPD 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 4
Data output delay time TPD 250 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF 4
Data output delay time TPD 400 ns 1.8V ≤ VCC < 2.5V, CL = 100 pF 4
Data output disable time TCZ 100 ns 4.5V ≤ VCC < 5.5V, (Note 1) 4
Data output disable time TCZ 200 ns 1.8V ≤ VCC < 4.5V, (Note 1) 4
Status valid time TSV 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 4
Status valid time TSV 300 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF 4
Status valid time TSV 500 ns 1.8V ≤ VCC < 2.5V, CL = 100 pF 4
Program cycle time TWC 6 ms Erase/Write mode (AA and LC versions) 5
ERAL cycle time TEC 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V 5
WRAL cycle time TWL 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Part Number VCC Range ORG Pin Word Size Temperature Ranges Packages 93AA56A 1.8V-5.5V No 8-bit I MC, MS, P, SN, OT, MN, ST 1

CAD (KiCad official)

  • Symbol: 93AA56CT-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 93aa56ct-i-etched.step / 93aa56ct-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 93aa56ct-i.step / 93aa56ct-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (42 pp, sha256 c5dbb77a34576a14, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF