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93AA46AE48T-I
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Microchip Tech EEPROM, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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93AA46AE48T-I
Microchip Tech · EEPROM · SOT-23-6
93AA46AE48T-I from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DO | output | Data Out outputs read data synchronously with CLK (TPD after the positive clock edge), shows Ready/Busy status during erase/write when CS is brought high after TCSL, and is High Z otherwise. |
| 2 | VSS | power_in | Ground reference for the device. |
| 3 | DI | input | Data In clocks in the Start bit, opcode, address and data synchronously with CLK. |
| 4 | CLK | input | Serial Clock synchronizes communication; opcodes, addresses and data are clocked in on its positive edge, and it is a don't-care while CS is low. |
| 5 | CS | input | A high level selects the device and a low level deselects it into Standby mode; CS must be low for 250 ns minimum (TCSL) between consecutive instructions. |
| 6 | VCC | power_in | Power supply input; the device is specified for VCC from 1.8 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Memory |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | 7 | V | 2 | |||
| All inputs and outputs w.r.t. VSS (absolute maximum, lower limit) | -0.6 | V | w.r.t. VSS | 2 | |||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Ambient temperature with power applied | -40 | 85 | °C | Power applied | 2 | ||
| ESD protection on all pins | 4 | kV | 2 | ||||
| Supply voltage (Industrial) | VCC | 1.8 | 5.5 | V | Industrial (I) range | 2 | |
| Ambient temperature (Industrial) | TA | -40 | 85 | °C | Industrial (I) range | 2 | |
| High-Level Input Voltage | VIH1 | 2 | V | VCC ≥ 2.7V | 2 | ||
| Low-Level Input Voltage | VIL1 | -0.3 | 0.8 | V | VCC ≥ 2.7V | 2 | |
| Low-Level Input Voltage | VIL2 | -0.3 | V | VCC 2.7V (relational symbol missing in source text) | 2 | ||
| Low-Level Output Voltage | VOL1 | 0.4 | V | IOL = 2.1 mA, VCC = 4.5V | 2 | ||
| Low-Level Output Voltage | VOL2 | 0.2 | V | IOL = 100 µA, VCC = 2.5V | 2 | ||
| High-Level Output Voltage | VOH1 | 2.4 | V | IOH = -400 µA, VCC = 4.5V | 2 | ||
| Input Leakage Current | ILI | -1 | 1 | µA | VIN = VSS or VCC | 2 | |
| Output Leakage Current | ILO | -1 | 1 | µA | VOUT = VSS or VCC | 2 | |
| Pin Capacitance (all inputs/outputs) | CIN, COUT | 7 | pF | VIN/VOUT = 0V (Note 1); TA = 25°C, FCLK = 1 MHz | 2 | ||
| Write Current | ICCWRITE | 2 | mA | VCC = 5.5V | 2 | ||
| Read Current | ICCREAD | 1 | mA | FCLK = 2 MHz, VCC = 5.5V | 2 | ||
| Read Current | ICCREAD | 500 | µA | FCLK = 2 MHz, VCC = 3.0V | 2 | ||
| Standby Current | ICCS | 1 | µA | CLK = CS = 0V; DI = VSS or VCC (Note 2) | 2 | ||
| Clock Frequency | FCLK | 2 | MHz | 2.5V ≤ VCC 5.5V | 3 | ||
| Clock Frequency | FCLK | 1 | MHz | 1.8V ≤ VCC 2.5V | 3 | ||
| Clock High Time | TCKH | 250 | ns | 2.5V ≤ VCC 5.5V | 3 | ||
| Clock High Time | TCKH | 450 | ns | 1.8V ≤ VCC 2.5V | 3 | ||
| Clock Low Time | TCKL | 200 | ns | 2.5V ≤ VCC 5.5V | 3 | ||
| Clock Low Time | TCKL | 450 | ns | 1.8V ≤ VCC 2.5V | 3 | ||
| Chip Select Setup Time | TCSS | 50 | ns | 4.5V ≤ VCC 5.5V | 3 | ||
| Chip Select Setup Time | TCSS | 100 | ns | 2.5V ≤ VCC 4.5V | 3 | ||
| Chip Select Setup Time | TCSS | 250 | ns | 1.8V ≤ VCC 2.5V | 3 | ||
| Chip Select Hold Time | TCSH | 0 | ns | 1.8V ≤ VCC 5.5V | 3 | ||
| Chip Select Low Time | TCSL | 250 | ns | 1.8V ≤ VCC 5.5V | 3 | ||
| Data Input Setup Time | TDIS | 100 | ns | 2.5V ≤ VCC 5.5V | 3 | ||
| Data Input Setup Time | TDIS | 250 | ns | 1.8V ≤ VCC 2.5V | 3 | ||
| Data Input Hold Time | TDIH | 100 | ns | 2.5V ≤ VCC 5.5V | 3 | ||
| Data Input Hold Time | TDIH | 250 | ns | 1.8V ≤ VCC 2.5V | 3 | ||
| Data Output Delay Time | TPD | 200 | ns | 4.5V ≤ VCC 5.5V, CL = 100 pF | 3 | ||
| Data Output Delay Time | TPD | 250 | ns | 2.5V ≤ VCC 4.5V, CL = 100 pF | 3 | ||
| Data Output Delay Time | TPD | 400 | ns | 1.8V ≤ VCC 2.5V, CL = 100 pF | 3 | ||
| Data Output Disable Time | TCZ | 100 | ns | 4.5V ≤ VCC 5.5V (Note 1) | 3 | ||
| Data Output Disable Time | TCZ | 200 | ns | 1.8V ≤ VCC 4.5V (Note 1) | 3 | ||
| Status Valid Time | TSV | 200 | ns | 4.5V ≤ VCC 5.5V, CL = 100 pF | 3 | ||
| Status Valid Time | TSV | 300 | ns | 2.5V ≤ VCC 4.5V, CL = 100 pF | 3 | ||
| Status Valid Time | TSV | 500 | ns | 1.8V ≤ VCC 2.5V, CL = 100 pF | 3 | ||
| Program Cycle Time | TWC | 6 | ms | Erase/Write mode | 3 | ||
| ERAL Cycle Time | TEC | 6 | ms | ERAL mode, 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| WRAL Cycle Time | TWL | 15 | ms | WRAL mode, 4.5V ≤ VCC ≤ 5.5V | 3 | ||
| Endurance | Endurance | 1 | M cycles | 25°C, VCC = 5.0V (Note 2) | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 | 14 |
CAD (KiCad official)
- Symbol:
93AA46AE48T-I - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
93aa46ae48t-i-etched.step/93aa46ae48t-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);93aa46ae48t-i.step/93aa46ae48t-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (24 pp, sha256
17292c6331b58f6a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 93AA46AE48T-I
**Microchip Tech** · EEPROM · SOT-23-6
93AA46AE48T-I from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DO | output | Data Out outputs read data synchronously with CLK (TPD after the positive clock edge), shows Ready/Busy status during erase/write when CS is brought high after TCSL, and is High Z otherwise. |
| 2 | VSS | power_in | Ground reference for the device. |
| 3 | DI | input | Data In clocks in the Start bit, opcode, address and data synchronously with CLK. |
| 4 | CLK | input | Serial Clock synchronizes communication; opcodes, addresses and data are clocked in on its positive edge, and it is a don't-care while CS is low. |
| 5 | CS | input | A high level selects the device and a low level deselects it into Standby mode; CS must be low for 250 ns minimum (TCSL) between consecutive instructions. |
| 6 | VCC | power_in | Power supply input; the device is specified for VCC from 1.8 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOT-23-6 |
| Category | Memory |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | | | 7 | V | | 2 |
| All inputs and outputs w.r.t. VSS (absolute maximum, lower limit) | | -0.6 | | | V | w.r.t. VSS | 2 |
| Storage temperature | | -65 | | 150 | °C | | 2 |
| Ambient temperature with power applied | | -40 | | 85 | °C | Power applied | 2 |
| ESD protection on all pins | | 4 | | | kV | | 2 |
| Supply voltage (Industrial) | VCC | 1.8 | | 5.5 | V | Industrial (I) range | 2 |
| Ambient temperature (Industrial) | TA | -40 | | 85 | °C | Industrial (I) range | 2 |
| High-Level Input Voltage | VIH1 | 2 | | | V | VCC ≥ 2.7V | 2 |
| Low-Level Input Voltage | VIL1 | -0.3 | | 0.8 | V | VCC ≥ 2.7V | 2 |
| Low-Level Input Voltage | VIL2 | -0.3 | | | V | VCC 2.7V (relational symbol missing in source text) | 2 |
| Low-Level Output Voltage | VOL1 | | | 0.4 | V | IOL = 2.1 mA, VCC = 4.5V | 2 |
| Low-Level Output Voltage | VOL2 | | | 0.2 | V | IOL = 100 µA, VCC = 2.5V | 2 |
| High-Level Output Voltage | VOH1 | 2.4 | | | V | IOH = -400 µA, VCC = 4.5V | 2 |
| Input Leakage Current | ILI | -1 | | 1 | µA | VIN = VSS or VCC | 2 |
| Output Leakage Current | ILO | -1 | | 1 | µA | VOUT = VSS or VCC | 2 |
| Pin Capacitance (all inputs/outputs) | CIN, COUT | | | 7 | pF | VIN/VOUT = 0V (Note 1); TA = 25°C, FCLK = 1 MHz | 2 |
| Write Current | ICCWRITE | | | 2 | mA | VCC = 5.5V | 2 |
| Read Current | ICCREAD | | | 1 | mA | FCLK = 2 MHz, VCC = 5.5V | 2 |
| Read Current | ICCREAD | | | 500 | µA | FCLK = 2 MHz, VCC = 3.0V | 2 |
| Standby Current | ICCS | | | 1 | µA | CLK = CS = 0V; DI = VSS or VCC (Note 2) | 2 |
| Clock Frequency | FCLK | | | 2 | MHz | 2.5V ≤ VCC 5.5V | 3 |
| Clock Frequency | FCLK | | | 1 | MHz | 1.8V ≤ VCC 2.5V | 3 |
| Clock High Time | TCKH | 250 | | | ns | 2.5V ≤ VCC 5.5V | 3 |
| Clock High Time | TCKH | 450 | | | ns | 1.8V ≤ VCC 2.5V | 3 |
| Clock Low Time | TCKL | 200 | | | ns | 2.5V ≤ VCC 5.5V | 3 |
| Clock Low Time | TCKL | 450 | | | ns | 1.8V ≤ VCC 2.5V | 3 |
| Chip Select Setup Time | TCSS | 50 | | | ns | 4.5V ≤ VCC 5.5V | 3 |
| Chip Select Setup Time | TCSS | 100 | | | ns | 2.5V ≤ VCC 4.5V | 3 |
| Chip Select Setup Time | TCSS | 250 | | | ns | 1.8V ≤ VCC 2.5V | 3 |
| Chip Select Hold Time | TCSH | 0 | | | ns | 1.8V ≤ VCC 5.5V | 3 |
| Chip Select Low Time | TCSL | 250 | | | ns | 1.8V ≤ VCC 5.5V | 3 |
| Data Input Setup Time | TDIS | 100 | | | ns | 2.5V ≤ VCC 5.5V | 3 |
| Data Input Setup Time | TDIS | 250 | | | ns | 1.8V ≤ VCC 2.5V | 3 |
| Data Input Hold Time | TDIH | 100 | | | ns | 2.5V ≤ VCC 5.5V | 3 |
| Data Input Hold Time | TDIH | 250 | | | ns | 1.8V ≤ VCC 2.5V | 3 |
| Data Output Delay Time | TPD | | | 200 | ns | 4.5V ≤ VCC 5.5V, CL = 100 pF | 3 |
| Data Output Delay Time | TPD | | | 250 | ns | 2.5V ≤ VCC 4.5V, CL = 100 pF | 3 |
| Data Output Delay Time | TPD | | | 400 | ns | 1.8V ≤ VCC 2.5V, CL = 100 pF | 3 |
| Data Output Disable Time | TCZ | | | 100 | ns | 4.5V ≤ VCC 5.5V (Note 1) | 3 |
| Data Output Disable Time | TCZ | | | 200 | ns | 1.8V ≤ VCC 4.5V (Note 1) | 3 |
| Status Valid Time | TSV | | | 200 | ns | 4.5V ≤ VCC 5.5V, CL = 100 pF | 3 |
| Status Valid Time | TSV | | | 300 | ns | 2.5V ≤ VCC 4.5V, CL = 100 pF | 3 |
| Status Valid Time | TSV | | | 500 | ns | 1.8V ≤ VCC 2.5V, CL = 100 pF | 3 |
| Program Cycle Time | TWC | | | 6 | ms | Erase/Write mode | 3 |
| ERAL Cycle Time | TEC | | | 6 | ms | ERAL mode, 4.5V ≤ VCC ≤ 5.5V | 3 |
| WRAL Cycle Time | TWL | | | 15 | ms | WRAL mode, 4.5V ≤ VCC ≤ 5.5V | 3 |
| Endurance | Endurance | 1 | | | M cycles | 25°C, VCC = 5.0V (Note 2) | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 | 14 |
## CAD (KiCad official)
- Symbol: `93AA46AE48T-I`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `93aa46ae48t-i-etched.step` / `93aa46ae48t-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `93aa46ae48t-i.step` / `93aa46ae48t-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588939782944657408) (24 pp, sha256 `17292c6331b58f6a`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/93aa46ae48t-i-datasheet.pdf)