component

8SLVP2108ANLGI8

Public Made by Adom

by adom

RENESAS Clock Buffers, Drivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing8slvp2108anlgi8factory-2.0.0extractor-text

Verified 8SLVP2108ANLGI8

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 8SLVP2108ANLGI8 · VQFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 23-page datasheet
  • ✓distributor: lcsc C2673032, digikey 6690-8SLVP2108ANLGI8TR-ND, mouser 972-8SLVP2108ANLGI8
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-y9tgwdcd/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 8slvp2108anlgi8.kicad_sym✓ 8slvp2108anlgi8.kicad_mod✓ 8slvp2108anlgi8.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
8slvp2108anlgi8 / README.md
History Download
Ray Publish 0.1.0 0f05060 2d ago

8SLVP2108ANLGI8

RENESAS · Clock Buffers, Drivers · VQFN-48-EP(7x7)

8SLVP2108ANLGI8 from RENESAS, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VEE power_in Negative supply pin (VEE = 0V).
2 nc unconnected Unused pin; do not connect.
3 PCLKB input Non-inverting LVPECL differential clock/data input for bank B with internal pulldown (51 kΩ typ).
4 nPCLKB input Inverting LVPECL differential clock input for bank B with internal pullup/pulldown (51 kΩ typ).
5 VREFB output Bias voltage reference for the PCLKB, nPCLKB input pair (VCC - 1.48V typ at IREF = 2mA, 3.3V supply).
6 VCC power_in Positive power supply pin (3.3V ± 5% or 2.5V ± 5%).
7 VCC power_in Positive power supply pin (3.3V ± 5% or 2.5V ± 5%).
8 VREFA output Bias voltage reference for the PCLKA, nPCLKA input pair (VCC - 1.48V typ at IREF = 2mA, 3.3V supply).
9 nPCLKA input Inverting LVPECL differential clock input for bank A with internal pullup/pulldown (51 kΩ typ).
10 PCLKA input Non-inverting LVPECL differential clock/data input for bank A with internal pulldown (51 kΩ typ).
11 nc unconnected Unused pin; do not connect.
12 VEE power_in Negative supply pin (VEE = 0V).
13 VCC power_in Positive power supply pin (3.3V ± 5% or 2.5V ± 5%).
14 QA0 output Non-inverting output of differential pair A0 with LVPECL interface levels.
15 nQA0 output Inverting output of differential pair A0 with LVPECL interface levels.
16 QA1 output Non-inverting output of differential pair A1 with LVPECL interface levels.
17 nQA1 output Inverting output of differential pair A1 with LVPECL interface levels.
18 QA2 output Non-inverting output of differential pair A2 with LVPECL interface levels.
19 nQA2 output Inverting output of differential pair A2 with LVPECL interface levels.
20 QA3 output Non-inverting output of differential pair A3 with LVPECL interface levels.
21 nQA3 output Inverting output of differential pair A3 with LVPECL interface levels.
22 QA4 output Non-inverting output of differential pair A4 with LVPECL interface levels.
23 nQA4 output Inverting output of differential pair A4 with LVPECL interface levels.
24 VCC power_in Positive power supply pin (3.3V ± 5% or 2.5V ± 5%).
25 QA5 output Non-inverting output of differential pair A5 with LVPECL interface levels.
26 nQA5 output Inverting output of differential pair A5 with LVPECL interface levels.
27 QA6 output Non-inverting output of differential pair A6 with LVPECL interface levels.
28 nQA6 output Inverting output of differential pair A6 with LVPECL interface levels.
29 QA7 output Non-inverting output of differential pair A7 with LVPECL interface levels.
30 nQA7 output Inverting output of differential pair A7 with LVPECL interface levels.
31 QB0 output Non-inverting output of differential pair B0 with LVPECL interface levels.
32 nQB0 output Inverting output of differential pair B0 with LVPECL interface levels.
33 QB1 output Non-inverting output of differential pair B1 with LVPECL interface levels.
34 nQB1 output Inverting output of differential pair B1 with LVPECL interface levels.
35 QB2 output Non-inverting output of differential pair B2 with LVPECL interface levels.
36 nQB2 output Inverting output of differential pair B2 with LVPECL interface levels.
37 VCC power_in Positive power supply pin (3.3V ± 5% or 2.5V ± 5%).
38 QB3 output Non-inverting output of differential pair B3 with LVPECL interface levels.
39 nQB3 output Inverting output of differential pair B3 with LVPECL interface levels.
40 QB4 output Non-inverting output of differential pair B4 with LVPECL interface levels.
41 nQB4 output Inverting output of differential pair B4 with LVPECL interface levels.
42 QB5 output Non-inverting output of differential pair B5 with LVPECL interface levels.
43 nQB5 output Inverting output of differential pair B5 with LVPECL interface levels.
44 QB6 output Non-inverting output of differential pair B6 with LVPECL interface levels.
45 nQB6 output Inverting output of differential pair B6 with LVPECL interface levels.
46 QB7 output Non-inverting output of differential pair B7 with LVPECL interface levels.
47 nQB7 output Inverting output of differential pair B7 with LVPECL interface levels.
48 VCC power_in Positive power supply pin (3.3V ± 5% or 2.5V ± 5%).
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package VQFN-48-EP(7x7)
Category Clock and Timing
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (3.3V) VCC 3.135 3.3 3.465 V Table 3A 3
Supply Voltage (2.5V) VCC 2.375 2.5 2.625 V Table 3B 3
Power Supply Current (3.3V) IEE 120 143 mA VCC = 3.3V ± 5% 3
Power Supply Current (2.5V) IEE 113 133 mA VCC = 2.5V ± 5% 3
Power Supply Current QA/QB (3.3V) ICC 595 706 mA QA[0:7] and QB[0:7] terminated 50 to VCC, 2V 3
Power Supply Current QA/QB (2.5V) ICC 594 705 mA QA[0:7] and QB[0:7] terminated 50 to VCC, 2V 3
Input High Current (3.3V) IIH 150 µA VCC = VIN = 3.465V 4
Input Low Current PCLKx (3.3V) IIL -10 µA VCC = 3.465V, VIN = 0V 4
Input Low Current nPCLKx (3.3V) IIL -150 µA VCC = 3.465V, VIN = 0V 4
Reference Voltage for Input Bias (3.3V) VREFx -1.82 -1.48 -1.27 V IREF = 2mA; printed as VCC, 1.82 / VCC, 1.48 / VCC, 1.27 4
Output High Voltage (3.3V) VOH -1.25 -1 -0.76 V Outputs terminated 50 to VCC, 2V; printed as VCC, 1.25 / VCC, 1.00 / VCC, 0.76 4
Output Low Voltage (3.3V) VOL -1.7 -1.47 -1.25 V Outputs terminated 50 to VCC, 2V; printed as VCC, 1.70 / VCC, 1.47 / VCC, 1.25 4
Input High Current (2.5V) IIH 150 µA VCC = VIN = 2.625V 4
Input Low Current PCLKx (2.5V) IIL -10 µA VCC = 2.625V, VIN = 0V 4
Input Low Current nPCLKx (2.5V) IIL -150 µA VCC = 2.625V, VIN = 0V 4
Reference Voltage for Input Bias (2.5V) VREFx -1.81 -1.47 -1.27 V IREF = 2mA; printed as VCC, 1.81 / VCC, 1.47 / VCC, 1.27 4
Output High Voltage (2.5V) VOH -1.26 -1 -0.75 V Outputs terminated 50 to VCC, 2V; printed as VCC, 1.26 / VCC, 1.00 / VCC, 0.75 4
Output Low Voltage (2.5V) VOL -1.67 -1.45 -1.22 V Outputs terminated 50 to VCC, 2V; printed as VCC, 1.67 / VCC, 1.45 / VCC, 1.22 4
Propagation Delay tPD 120 255 390 ps PCLKx to Qx, VPP=0.1V or 0.3V 5
Output Skew tsk(o) 29 63 ps 5
Output Bank Skew tsk(b) 15 43 ps 5
Pulse Skew tsk(p) 4 25 ps 5
Part-to-Part Skew tsk(pp) 70 154 ps 5
Output Rise/Fall Time tR / tF 60 100 165 ps 20% to 80% 5
Input Frequency fREF 2 GHz PCLKx, nPCLKx 5
Input Edge Rate V/t 1.5 V/ns PCLKx, nPCLKx 5
Differential Input Voltage VPP 0.1 1.5 V fREF < 1.5GHz 5
Differential Input Voltage VPP 0.2 1.5 V fREF ≥ 1.5GHz 5
Common Mode Input Voltage VCMR 1 V max printed VCC, 0.3 5
Output Voltage Swing, Peak-to-Peak (2.5V) VO(pp) 0.29 0.46 0.63 V fREF ≤ 2GHz, VCC = 2.5V ± 5% 5
Output Voltage Swing, Peak-to-Peak (3.3V) VO(pp) 0.31 0.48 0.67 V fREF ≤ 2GHz, VCC = 3.3V ± 5% 5
Differential Output Voltage Swing (2.5V) VDIFF_OUT 0.58 0.92 1.26 V fREF ≤ 2GHz, VCC = 2.5V ± 5% 5
Differential Output Voltage Swing (3.3V) VDIFF_OUT 0.62 0.96 1.34 V fREF ≤ 2GHz, VCC = 3.3V ± 5% 5
Additive Phase Jitter RMS (3.3V) tJIT 46 54 fs fREF = 156.25MHz Square Wave, VPP = 1V, 12kHz, 20MHz 6
Additive Phase Jitter RMS (2.5V) tJIT 48 57 fs fREF = 156.25MHz Square Wave, VPP = 1V, 12kHz, 20MHz 6
Spurious Suppression tJIT, SP -55 dB fQB0 = 500MHz, VPP(PCLKB) = 0.15V, VCMR(PCLKB) = 1V; fQA7 = 62.5MHz, VPP(PCLKA) = 1V, VCMR(PCLKA) = 1V 5
Spurious Suppression tJIT, SP -65 dB fQB0 = 500MHz, VPP(PCLKB) = 0.15V, VCMR(PCLKB) = 1V; fQA7 = 15.625MHz, VPP(PCLKA) = 1V, VCMR(PCLKA) = 1V 5
Ambient air temperature TA -40 85 °C 3
Junction temperature TJ 125 °C 3
Supply Voltage VCC 4.6 V 3
Inputs VI -0.5 V -0.5V to VCC + 0.5V 3
Output Continuous Current (LVPECL) IO 50 mA Continuous 3
Output Surge Current (LVPECL) IO 100 mA Surge 3
Input Sink/Source IREF -2 2 mA 3
Maximum Junction Temperature TJ,MAX 150 °C 3
Storage Temperature TSTG -65 150 °C 3
ESD - Human Body Model 2000 V 3
ESD - Charged Device Model 1500 V 3
Thermal Resistance Junction-to-Ambient θJA 30.5 °C/W 0 m/s, multi-layer PCB 16
Thermal Resistance Junction-to-Ambient θJA 26.7 °C/W 1 m/s, multi-layer PCB 16
Thermal Resistance Junction-to-Ambient θJA 23.9 °C/W 2.5 m/s, multi-layer PCB 16
Junction-to-board thermal characterization parameter ΨJB 1 °C/W 18
Input Capacitance CIN 2 pF 2
Input Pulldown Resistor RPULLDOWN 51 kΩ 2
Input Pullup Resistor RPULLUP 51 kΩ 2

CAD (KiCad official)

  • Symbol: 8SLVP2108ANLGI8
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: 8slvp2108anlgi8-etched.step / 8slvp2108anlgi8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 8slvp2108anlgi8.step / 8slvp2108anlgi8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (23 pp, sha256 70173cce8e9b77fb, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF