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8533AGI-01LFT

Public Made by Adom

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RENESAS Clock Buffers, Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing8533agi-01lftfactory-2.0.0extractor-text

Verified 8533AGI-01LFT

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 8533AGI-01LFT · TSSOP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 19-page datasheet
  • ✓distributor: lcsc C2673002, digikey 6690-8533AGI-01LFTTR-ND, mouser 972-8533AGI-01LFT
  • ✓family: TSSOP-20_4.4x6.5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-fgg3pf4e/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.15)
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 8533agi-01lft.kicad_sym✓ 8533agi-01lft.kicad_mod✓ 8533agi-01lft.step
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Ray Publish 0.1.0 9e244a7 3d ago

8533AGI-01LFT

RENESAS · Clock Buffers, Drivers · TSSOP-20

8533AGI-01LFT from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VEE power_in Negative supply pin.
2 CLK_EN input Synchronizing clock enable with internal pull-up; when HIGH the clock outputs follow the clock input, and when LOW Q outputs are forced low and nQ outputs forced high, with LVCMOS/LVTTL interface levels.
3 CLK_SEL input Clock select with internal pull-down; when HIGH it selects PCLK/nPCLK inputs and when LOW it selects CLK/nCLK inputs, with LVCMOS/LVTTL interface levels.
4 CLK input Non-inverting differential clock input with internal pull-down, accepting LVDS, LVPECL, LVHSTL, SSTL and HCSL levels.
5 nCLK input Inverting differential clock input with internal pull-up, accepting LVDS, LVPECL, LVHSTL, SSTL and HCSL levels.
6 PCLK input Non-inverting differential LVPECL clock input with internal pull-down, accepting LVPECL, CML and SSTL levels.
7 nPCLK input Inverting differential LVPECL clock input with internal pull-up, accepting LVPECL, CML and SSTL levels.
8 nc unconnected No connect.
9 nc unconnected No connect.
10 VCC power_in Positive supply pin; VCC is specified at 3.135 V to 3.465 V (3.3 V ±5%).
11 nQ3 output Inverting differential LVPECL output of pair 3, designed to drive 50Ω transmission lines with termination to VCC - 2V.
12 Q3 output Non-inverting differential LVPECL output of pair 3, designed to drive 50Ω transmission lines with termination to VCC - 2V.
13 VCC power_in Positive supply pin; VCC is specified at 3.135 V to 3.465 V (3.3 V ±5%).
14 nQ2 output Inverting differential LVPECL output of pair 2, designed to drive 50Ω transmission lines with termination to VCC - 2V.
15 Q2 output Non-inverting differential LVPECL output of pair 2, designed to drive 50Ω transmission lines with termination to VCC - 2V.
16 nQ1 output Inverting differential LVPECL output of pair 1, designed to drive 50Ω transmission lines with termination to VCC - 2V.
17 Q1 output Non-inverting differential LVPECL output of pair 1, designed to drive 50Ω transmission lines with termination to VCC - 2V.
18 VCC power_in Positive supply pin; VCC is specified at 3.135 V to 3.465 V (3.3 V ±5%).
19 nQ0 output Inverting differential LVPECL output of pair 0, designed to drive 50Ω transmission lines with termination to VCC - 2V.
20 Q0 output Non-inverting differential LVPECL output of pair 0, designed to drive 50Ω transmission lines with termination to VCC - 2V.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-20
Category Clock and Timing
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive Supply Voltage VCC 3.135 3.3 3.465 V 4
Power Supply Current IEE 52 mA 4
Input High Voltage (LVCMOS control pins) VIH 2 V 4
Input Low Voltage (LVCMOS control pins) VIL -0.3 0.8 V 4
Input High Current CLK_EN IIH 5 µA VIN = VCC = 3.465V 4
Input High Current CLK_SEL IIH 150 µA VIN = VCC = 3.465V 4
Input Low Current CLK_EN IIL -150 µA VIN = 0V, VCC = 3.465V 4
Input Low Current CLK_SEL IIL -5 µA VIN = 0V, VCC = 3.465V 4
Input High Current nCLK IIH 5 µA VCC = VIN = 3.465V 4
Input High Current CLK IIH 150 µA VCC = VIN = 3.465V 4
Input Low Current nCLK IIL -150 µA VCC = 3.465V, VIN = 0V 4
Input Low Current CLK IIL -5 µA VCC = 3.465V, VIN = 0V 4
Peak-to-Peak Input Voltage (CLK/nCLK) VPP 0.15 1.3 V 4
Input High Current PCLK IIH 150 µA VCC = VIN = 3.465V 5
Input High Current nPCLK IIH 5 µA VCC = VIN = 3.465V 5
Input Low Current PCLK IIL -5 µA VCC = 3.465V, VIN = 0V 5
Input Low Current nPCLK IIL -150 µA VCC = 3.465V, VIN = 0V 5
Peak-to-Peak Input Voltage (PCLK/nPCLK) VPP 0.3 1 V 5
Peak-to-Peak Output Voltage Swing VSWING 0.6 1 V 5
Output Frequency fMAX 650 MHz 5
Propagation Delay CLK, nCLK tPD 1.15 1.5 ns NOTE 1 (differential input to differential output crossing point) 5
Propagation Delay PCLK, nPCLK tPD 1 1.3 ns NOTE 1 (differential input to differential output crossing point) 5
Output Skew tsk(o) 30 ps NOTE 2, 4 5
Part-to-Part Skew tsk(pp) 150 ps NOTE 3, 4 5
Output Rise/Fall Time tR / tF 300 800 ps 5
Output Duty Cycle odc 47 53 % 5
Input Capacitance CIN 4 pF 2
Input Pullup Resistor RPULLUP 51 kΩ 2
Input Pulldown Resistor RPULLDOWN 51 kΩ 2
Supply Voltage VCC 4.6 V 4
Inputs (VI, range -0.5V to VCC + 0.5V) VI -0.5 V 4
Outputs Continuous Current IO 50 mA 4
Outputs Surge Current IO 100 mA 4
Storage Temperature TSTG -65 150 °C 4
Ambient Operating Temperature TA -40 85 °C 1
Maximum Recommended Junction Temperature Tj 125 °C 12
Package Thermal Impedance, junction-to-ambient θJA 73.2 °C/W 0 lfpm 4
Thermal Resistance θJA, multi-layer PCB θJA 73.2 °C/W Multi-layer PCB, JEDEC, 0 lfpm 12
Thermal Resistance θJA, multi-layer PCB θJA 66.6 °C/W Multi-layer PCB, JEDEC, 200 lfpm 12
Thermal Resistance θJA, multi-layer PCB θJA 63.5 °C/W Multi-layer PCB, JEDEC, 500 lfpm 12
Thermal Resistance θJA, single-layer PCB θJA 114.5 °C/W Single-layer PCB, JEDEC, 0 lfpm 12
Thermal Resistance θJA, single-layer PCB θJA 98 °C/W Single-layer PCB, JEDEC, 200 lfpm 12
Thermal Resistance θJA, single-layer PCB θJA 88 °C/W Single-layer PCB, JEDEC, 500 lfpm 12

CAD (KiCad official)

  • Symbol: 8533AGI-01LFT
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 8533agi-01lft-etched.step / 8533agi-01lft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 8533agi-01lft.step / 8533agi-01lft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (19 pp, sha256 d5dbe9589dbdb190, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF