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85314BGI-01LF

RENESAS · Clock Buffers, Drivers · TSSOP-20

85314BGI-01LF from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q0 output Non-inverting output of differential pair 0 with LVPECL interface levels.
2 nQ0 output Inverting output of differential pair 0 with LVPECL interface levels.
3 Q1 output Non-inverting output of differential pair 1 with LVPECL interface levels.
4 nQ1 output Inverting output of differential pair 1 with LVPECL interface levels.
5 Q2 output Non-inverting output of differential pair 2 with LVPECL interface levels.
6 nQ2 output Inverting output of differential pair 2 with LVPECL interface levels.
7 Q3 output Non-inverting output of differential pair 3 with LVPECL interface levels.
8 nQ3 output Inverting output of differential pair 3 with LVPECL interface levels.
9 Q4 output Non-inverting output of differential pair 4 with LVPECL interface levels.
10 nQ4 output Inverting output of differential pair 4 with LVPECL interface levels.
11 VEE power_in Negative supply pin, VEE = 0V.
12 CLK_SEL input Clock select input with internal pulldown; HIGH selects CLK1, LOW selects CLK0/nCLK0, LVTTL/LVCMOS levels.
13 nc unconnected No connect.
14 nCLK0 input Inverting differential clock input with internal pullup.
15 CLK0 input Non-inverting differential clock input with internal pulldown.
16 CLK1 input Single-ended clock input with internal pulldown, LVTTL/LVCMOS interface levels.
17 nc unconnected No connect.
18 VCC power_in Positive supply pin, VCC = 2.375V to 3.8V.
19 nCLK_EN input Synchronizing clock enable with internal pulldown; LOW lets outputs follow clock input, HIGH forces Q low and nQ high, LVTTL/LVCMOS levels.
20 VCC power_in Positive supply pin, VCC = 2.375V to 3.8V.

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-20
Category Clock and Timing
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage VCC 2.375 3.3 3.8 V VEE = 0V 4
Power Supply Current IEE 80 mA 4
Input High Voltage nCLK_EN, CLK_SEL VIH 2 V nCLK_EN, CLK_SEL 4
Input High Voltage CLK1 VIH 2 V CLK1 4
Input Low Voltage nCLK_EN, CLK_SEL VIL -0.3 0.8 V nCLK_EN, CLK_SEL 4
Input Low Voltage CLK1 VIL -0.3 1.3 V CLK1 4
Input High Current CLK1, CLK_SEL, nCLK_EN IIH 150 µA VIN = VCC = 3.8V 4
Input Low Current CLK1, CLK_SEL, nCLK_EN IIL -5 µA VCC = 3.8V, VIN = 0V 4
Input High Current nCLK0 IIH 5 µA VCC = VIN = 3.8V 4
Input High Current CLK0 IIH 150 µA VCC = VIN = 3.8V 4
Input Low Current nCLK0 IIL -150 µA VCC = 3.8V, VIN = 0V 4
Input Low Current CLK0 IIL -5 µA VCC = 3.8V, VIN = 0V 4
Peak-to-Peak Input Voltage VPP 0.15 1.3 V 4
Common Mode Input Voltage VCMR 0.5 V NOTE 1, 2 4
Peak-to-Peak Output Voltage Swing VSWING 0.6 1 V 5
Output Frequency CLK0, nCLK0 fMAX 700 MHz CLK0, nCLK0 5
Output Frequency CLK1 fMAX 300 MHz CLK1 5
Propagation Delay, Low to High tpLH 1 1.4 1.8 ns NOTE 1 5
Output Skew TSSOP tsk(o) 30 ps TSSOP Package; NOTE 3, 6 5
Part-to-Part Skew tsk(pp) 350 ps NOTE 4, 6 5
Output Rise/Fall Time tR / tF 200 700 ps 20% to 80% 5
Output Duty Cycle CLK0, nCLK0 odc 45 55 % CLK0, nCLK0 ƒ ≤ 700MHz 5
Output Duty Cycle CLK1 odc 45 55 % CLK1 ƒ ≤ 250MHz 5
RMS Phase Jitter (Random) tjit(Ø) 0.05 ps Integration Range: (12kHz - 20MHz) 5
Input Capacitance CIN 4 pF 2
Input Pullup Resistor RPULLUP 51 kΩ 2
Input Pulldown Resistor RPULLDOWN 51 kΩ 2
Supply Voltage VCC 4.6 V 4
Inputs VI -0.5 V -0.5V to VCC + 0.5V 4
Output Continuous Current IO 50 mA Continuous Current 4
Output Surge Current IO 100 mA Surge Current 4
Storage Temperature TSTG -65 150 °C 4
Ambient Operating Temperature TA -40 85 °C 1
Package Thermal Impedance, 20 Lead TSSOP θJA 73.2 °C/W 0 lfpm 4

CAD (KiCad official)

  • Symbol: 85314BGI-01LF
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 85314bgi-01lf-etched.step / 85314bgi-01lf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 85314bgi-01lf.step / 85314bgi-01lf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (21 pp, sha256 3c7b07c6943cb885, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF