8413S12BKILF

{
  "slug": "8413s12bkilf",
  "version": "0.1.0",
  "type": "component",
  "description": "RENESAS Clock Generators / Frequency Synthesizers / PLL, QFN-72-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "clock and timing",
    "8413s12bkilf",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "8413s12bkilf.kicad_sym",
    "8413s12bkilf.kicad_mod",
    "8413s12bkilf.glb",
    "8413s12bkilf.step",
    "8413s12bkilf.lbr",
    "docs/hero.png",
    "docs/8413s12bkilf-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "8413s12bkilf-hero.glb",
    "8413s12bkilf-hero.overlay.json",
    "8413s12bkilf-etched.glb"
  ],
  "component": {
    "mpn": "8413S12BKILF",
    "manufacturer": "RENESAS",
    "package": "QFN-72-EP(10x10)",
    "pin_count": 73,
    "category": "Clock and Timing",
    "subcategory": "Clock Generators / Frequency Synthesizers / PLL",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/ff941717d2aa756ede750cc5d5724c74.pdf",
    "parts": {
      "symbol": "8413s12bkilf.kicad_sym",
      "footprint": "8413s12bkilf.kicad_mod",
      "model_3d": "8413s12bkilf-hero.glb",
      "model_3d_plain": "8413s12bkilf-etched.glb",
      "model_3d_step": "8413s12bkilf-etched.step",
      "model_3d_step_plain": "8413s12bkilf.step",
      "lbr": "8413s12bkilf.lbr"
    },
    "distributor_links": {
      "lcsc": "C1519957",
      "digikey": "6690-8413S12BKILF-ND",
      "mouser": "972-8413S12BKILF"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T22:43:07Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "6690-8413S12BKILF-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "972-8413S12BKILF",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "GND",
        "type": "power_in",
        "description": "Power supply ground."
      },
      {
        "number": "2",
        "name": "FSEL_A0",
        "type": "input",
        "description": "Selects the QAx/nQAx output frequency (00 = 100 MHz, 01 = 125 MHz, 10 = 156.25 MHz, 11 = 312.5 MHz); pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "3",
        "name": "FSEL_A1",
        "type": "input",
        "description": "Selects the QAx/nQAx output frequency together with FSEL_A0; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "4",
        "name": "FSEL_B0",
        "type": "input",
        "description": "Selects the QBx/nQBx output frequency together with FSEL_B1; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "5",
        "name": "FSEL_B1",
        "type": "input",
        "description": "Selects the QBx/nQBx output frequency together with FSEL_B0; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "6",
        "name": "FSEL_C0",
        "type": "input",
        "description": "Selects the QCx/nQCx output frequency together with FSEL_C1; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "7",
        "name": "FSEL_C1",
        "type": "input",
        "description": "Selects the QCx/nQCx output frequency together with FSEL_C0; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "8",
        "name": "FSEL_D0",
        "type": "input",
        "description": "Selects the QDx/nQDx output frequency together with FSEL_D1; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "9",
        "name": "FSEL_D1",
        "type": "input",
        "description": "Selects the QDx/nQDx output frequency together with FSEL_D0; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "10",
        "name": "FSEL_E0",
        "type": "input",
        "description": "Selects the QEx/nQEx output frequency together with FSEL_E1; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "11",
        "name": "VDDA",
        "type": "power_in",
        "description": "Analog supply pin for the internal PLL."
      },
      {
        "number": "12",
        "name": "FSEL_E1",
        "type": "input",
        "description": "Selects the QEx/nQEx output frequency together with FSEL_E0; pulldown, LVCMOS/LVTTL levels."
      },
      {
        "number": "13",
        "name": "nc",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "14",
        "name": "XTAL_IN",
        "type": "input",
        "description": "Input of the parallel resonant crystal interface (25 MHz crystal or external 25 MHz source)."
      },
      {
        "number": "15",
        "name": "XTAL_OUT",
        "type": "output",
        "description": "Output of the parallel resonant crystal interface."
      },
      {
        "number": "16",
        "name": "nc",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "17",
        "name": "REF_SEL",
        "type": "input",
        "description": "Input source control: LOW selects CLK/nCLK, HIGH (default, pullup) selects XTAL_IN/XTAL_OUT; LVCMOS/LVTTL levels."
      },
      {
        "number": "18",
        "name": "GND",
        "type": "power_in",
        "description": "Power supply ground."
      },
      {
        "number": "19",
        "name": "nc",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "20",
        "name": "VDD",
        "type": "power_in",
        "description": "Core supply pin."
      },
      {
        "number": "21",
        "name": "PLL_SEL",
        "type": "input",
        "description": "PLL bypass control: LOW selects PLL bypass, HIGH (default, pullup) selects PLL mode; LVCMOS/LVTTL levels."
      },
      {
        "number": "22",
        "name": "CLK",
        "type": "input",
        "description": "Non-inverting differential clock input (LVPECL, LVDS, LVHSTL, HCSL levels accepted); pulldown."
      },
      {
        "number": "23",
        "name": "nCLK",
        "type": "input",
        "description": "Inverting differential clock input with internal resistor bias to VDD/2, allowing single-ended LVCMOS/LVTTL drive of CLK."
      },
      {
        "number": "24",
        "name": "OE_A",
        "type": "input",
        "description": "Active HIGH output enable for Bank A outputs (pullup); LOW puts QA outputs in high impedance."
      },
      {
        "number": "25",
        "name": "VDDO_A",
        "type": "power_in",
        "description": "Bank A (HCSL) output supply pin, 3.3 V."
      },
      {
        "number": "26",
        "name": "QA0",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "27",
        "name": "nQA0",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "28",
        "name": "QA1",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "29",
        "name": "nQA1",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "30",
        "name": "OE_B",
        "type": "input",
        "description": "Active HIGH output enable for Bank B outputs (pullup); LOW puts QB outputs in high impedance."
      },
      {
        "number": "31",
        "name": "QB0",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "32",
        "name": "nQB0",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "33",
        "name": "QB1",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "34",
        "name": "nQB1",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "35",
        "name": "VDDO_B",
        "type": "power_in",
        "description": "Bank B (HCSL) output supply pin, 3.3 V."
      },
      {
        "number": "36",
        "name": "nc",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "37",
        "name": "nc",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "38",
        "name": "GND",
        "type": "power_in",
        "description": "Power supply ground."
      },
      {
        "number": "39",
        "name": "VDD",
        "type": "power_in",
        "description": "Core supply pin."
      },
      {
        "number": "40",
        "name": "OE_C",
        "type": "input",
        "description": "Active HIGH output enable for Bank C outputs (pullup); LOW puts QC outputs in high impedance."
      },
      {
        "number": "41",
        "name": "QC0",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "42",
        "name": "nQC0",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "43",
        "name": "QC1",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "44",
        "name": "nQC1",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "45",
        "name": "VDDO_C",
        "type": "power_in",
        "description": "Bank C (HCSL) output supply pin, 3.3 V."
      },
      {
        "number": "46",
        "name": "VDDO_D",
        "type": "power_in",
        "description": "Bank D (HCSL) output and HCSL reference circuit supply pin; must be connected to 3.3 V to use any HCSL output."
      },
      {
        "number": "47",
        "name": "QD0",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "48",
        "name": "nQD0",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "49",
        "name": "QD1",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "50",
        "name": "nQD1",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "51",
        "name": "OE_D",
        "type": "input",
        "description": "Active HIGH output enable for Bank D outputs (pullup); LOW puts QD outputs in high impedance."
      },
      {
        "number": "52",
        "name": "IREF",
        "type": "input",
        "description": "External fixed precision resistor (475) from this pin to ground sets the reference current for the differential current-mode Q[Ax:Ex] outputs."
      },
      {
        "number": "53",
        "name": "VDD",
        "type": "power_in",
        "description": "Core supply pin."
      },
      {
        "number": "54",
        "name": "nc",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "55",
        "name": "nc",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "56",
        "name": "VDDO_E",
        "type": "power_in",
        "description": "Bank E (HCSL) output supply pin, 3.3 V."
      },
      {
        "number": "57",
        "name": "QE0",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "58",
        "name": "nQE0",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "59",
        "name": "QE1",
        "type": "output",
        "description": "Differential output pair (true), HCSL interface levels."
      },
      {
        "number": "60",
        "name": "nQE1",
        "type": "output",
        "description": "Differential output pair (complement), HCSL interface levels."
      },
      {
        "number": "61",
        "name": "OE_E",
        "type": "input",
        "description": "Active HIGH output enable for Bank E outputs (pullup); LOW puts QE outputs in high impedance."
      },
      {
        "number": "62",
        "name": "nMR",
        "type": "input",
        "description": "Active LOW master reset: when LOW all Qx go low and nQx go high, when HIGH all outputs are enabled (pullup, LVCMOS/LVTTL levels)."
      },
      {
        "number": "63",
        "name": "VDDO_F",
        "type": "power_in",
        "description": "QF output supply pin (LVCMOS/LVTTL), 3.3 V."
      },
      {
        "number": "64",
        "name": "QF",
        "type": "output",
        "description": "Single-ended output, 3.3 V LVCMOS/LVTTL interface levels."
      },
      {
        "number": "65",
        "name": "VDDO_G",
        "type": "power_in",
        "description": "QG output supply pin (LVCMOS/LVTTL), 3.3 V or 2.5 V."
      },
      {
        "number": "66",
        "name": "QG",
        "type": "output",
        "description": "Single-ended output, 3.3 V or 2.5 V LVCMOS/LVTTL interface levels."
      },
      {
        "number": "67",
        "name": "OE_G",
        "type": "input",
        "description": "Active HIGH output enable for the QG output (pullup); LOW puts QG in high impedance."
      },
      {
        "number": "68",
        "name": "OE_REF",
        "type": "input",
        "description": "Active HIGH output enable for QREF[0:1] outputs (pullup); LOW puts QREF outputs in high impedance."
      },
      {
        "number": "69",
        "name": "QREF0",
        "type": "output",
        "description": "Single-ended REF output, 3.3 V or 2.5 V LVCMOS/LVTTL interface levels."
      },
      {
        "number": "70",
        "name": "QREF1",
        "type": "output",
        "description": "Single-ended REF output, 3.3 V or 2.5 V LVCMOS/LVTTL interface levels."
      },
      {
        "number": "71",
        "name": "VDDO_QREF",
        "type": "power_in",
        "description": "QREF[0:1] output supply pin (LVCMOS/LVTTL), 3.3 V or 2.5 V."
      },
      {
        "number": "72",
        "name": "nc",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "73",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The 10x10 mm body size in the package hint is not stated in the supplied text. The package outline (; The exposed pad (EPAD / heat slug, ground) is described in the text but has no pin number given, so ; Table 1 lists XTAL_IN and XTAL_OUT together as 'Input', but the text says XTAL_OUT is the output. XT",
          "exposed pad 73 added from the footprint"
        ],
        "pages_sent": 12,
        "cost_usd": 0.1124,
        "at": "2026-10-30T22:42:26"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/ff941717d2aa756ede750cc5d5724c74.pdf",
        "pages": 34,
        "sha256": "f5f33d24430b1859",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 73,
        "described": 73,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "8413s12bkilf.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.02,
          10.02,
          0.9
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3c075db71112d42a4cb0ec2b0778a3ebc00cd430ebc70435737dec5034ba9a14",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "8413s12bkilf-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.02,
          10.02,
          0.9
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "18987da4cf3037d451e653753b0ce073882b7aa7105378a7e98ebfcf663e5597",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "72 Lead VFQFN (K suffix)",
      "source_page": 29,
      "D": {
        "nom_mm": 9.75,
        "range_mm": [
          null,
          null
        ]
      },
      "E1": {
        "nom_mm": 9.75,
        "range_mm": [
          null,
          null
        ]
      },
      "e": {
        "nom_mm": 0.5,
        "range_mm": [
          null,
          null
        ]
      },
      "A": {
        "nom_mm": 0.9,
        "range_mm": [
          0.8,
          1.0
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "8413s12bkilf.step",
        "verdict": "PASS",
        "reasons": [
          "height within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}