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8413S12BKILF

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RENESAS Clock Generators / Frequency Synthesizers / PLL, QFN-72-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing8413s12bkilffactory-2.0.0extractor-text

Verified 8413S12BKILF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 73 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 8413S12BKILF · QFN-72-EP(10x10) · 73 pins
  • ✓copper: 73 copper pads, none touching another net
  • ✓datasheet: all 73 pin names found in the 34-page datasheet
  • ✓distributor: lcsc C1519957, digikey 6690-8413S12BKILF-ND, mouser 972-8413S12BKILF
  • ✓family: QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qlye54sw/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.29)
  • ✓pads: 73 pins = 73 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 73 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 8413s12bkilf.kicad_sym✓ 8413s12bkilf.kicad_mod✓ 8413s12bkilf.step
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8413S12BKILF

RENESAS · Clock Generators / Frequency Synthesizers / PLL · QFN-72-EP(10x10)

8413S12BKILF from RENESAS, in a QFN-72-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Power supply ground.
2 FSEL_A0 input Selects the QAx/nQAx output frequency (00 = 100 MHz, 01 = 125 MHz, 10 = 156.25 MHz, 11 = 312.5 MHz); pulldown, LVCMOS/LVTTL levels.
3 FSEL_A1 input Selects the QAx/nQAx output frequency together with FSEL_A0; pulldown, LVCMOS/LVTTL levels.
4 FSEL_B0 input Selects the QBx/nQBx output frequency together with FSEL_B1; pulldown, LVCMOS/LVTTL levels.
5 FSEL_B1 input Selects the QBx/nQBx output frequency together with FSEL_B0; pulldown, LVCMOS/LVTTL levels.
6 FSEL_C0 input Selects the QCx/nQCx output frequency together with FSEL_C1; pulldown, LVCMOS/LVTTL levels.
7 FSEL_C1 input Selects the QCx/nQCx output frequency together with FSEL_C0; pulldown, LVCMOS/LVTTL levels.
8 FSEL_D0 input Selects the QDx/nQDx output frequency together with FSEL_D1; pulldown, LVCMOS/LVTTL levels.
9 FSEL_D1 input Selects the QDx/nQDx output frequency together with FSEL_D0; pulldown, LVCMOS/LVTTL levels.
10 FSEL_E0 input Selects the QEx/nQEx output frequency together with FSEL_E1; pulldown, LVCMOS/LVTTL levels.
11 VDDA power_in Analog supply pin for the internal PLL.
12 FSEL_E1 input Selects the QEx/nQEx output frequency together with FSEL_E0; pulldown, LVCMOS/LVTTL levels.
13 nc unconnected No connect.
14 XTAL_IN input Input of the parallel resonant crystal interface (25 MHz crystal or external 25 MHz source).
15 XTAL_OUT output Output of the parallel resonant crystal interface.
16 nc unconnected No connect.
17 REF_SEL input Input source control: LOW selects CLK/nCLK, HIGH (default, pullup) selects XTAL_IN/XTAL_OUT; LVCMOS/LVTTL levels.
18 GND power_in Power supply ground.
19 nc unconnected No connect.
20 VDD power_in Core supply pin.
21 PLL_SEL input PLL bypass control: LOW selects PLL bypass, HIGH (default, pullup) selects PLL mode; LVCMOS/LVTTL levels.
22 CLK input Non-inverting differential clock input (LVPECL, LVDS, LVHSTL, HCSL levels accepted); pulldown.
23 nCLK input Inverting differential clock input with internal resistor bias to VDD/2, allowing single-ended LVCMOS/LVTTL drive of CLK.
24 OE_A input Active HIGH output enable for Bank A outputs (pullup); LOW puts QA outputs in high impedance.
25 VDDO_A power_in Bank A (HCSL) output supply pin, 3.3 V.
26 QA0 output Differential output pair (true), HCSL interface levels.
27 nQA0 output Differential output pair (complement), HCSL interface levels.
28 QA1 output Differential output pair (true), HCSL interface levels.
29 nQA1 output Differential output pair (complement), HCSL interface levels.
30 OE_B input Active HIGH output enable for Bank B outputs (pullup); LOW puts QB outputs in high impedance.
31 QB0 output Differential output pair (true), HCSL interface levels.
32 nQB0 output Differential output pair (complement), HCSL interface levels.
33 QB1 output Differential output pair (true), HCSL interface levels.
34 nQB1 output Differential output pair (complement), HCSL interface levels.
35 VDDO_B power_in Bank B (HCSL) output supply pin, 3.3 V.
36 nc unconnected No connect.
37 nc unconnected No connect.
38 GND power_in Power supply ground.
39 VDD power_in Core supply pin.
40 OE_C input Active HIGH output enable for Bank C outputs (pullup); LOW puts QC outputs in high impedance.
41 QC0 output Differential output pair (true), HCSL interface levels.
42 nQC0 output Differential output pair (complement), HCSL interface levels.
43 QC1 output Differential output pair (true), HCSL interface levels.
44 nQC1 output Differential output pair (complement), HCSL interface levels.
45 VDDO_C power_in Bank C (HCSL) output supply pin, 3.3 V.
46 VDDO_D power_in Bank D (HCSL) output and HCSL reference circuit supply pin; must be connected to 3.3 V to use any HCSL output.
47 QD0 output Differential output pair (true), HCSL interface levels.
48 nQD0 output Differential output pair (complement), HCSL interface levels.
49 QD1 output Differential output pair (true), HCSL interface levels.
50 nQD1 output Differential output pair (complement), HCSL interface levels.
51 OE_D input Active HIGH output enable for Bank D outputs (pullup); LOW puts QD outputs in high impedance.
52 IREF input External fixed precision resistor (475) from this pin to ground sets the reference current for the differential current-mode Q[Ax:Ex] outputs.
53 VDD power_in Core supply pin.
54 nc unconnected No connect.
55 nc unconnected No connect.
56 VDDO_E power_in Bank E (HCSL) output supply pin, 3.3 V.
57 QE0 output Differential output pair (true), HCSL interface levels.
58 nQE0 output Differential output pair (complement), HCSL interface levels.
59 QE1 output Differential output pair (true), HCSL interface levels.
60 nQE1 output Differential output pair (complement), HCSL interface levels.
61 OE_E input Active HIGH output enable for Bank E outputs (pullup); LOW puts QE outputs in high impedance.
62 nMR input Active LOW master reset: when LOW all Qx go low and nQx go high, when HIGH all outputs are enabled (pullup, LVCMOS/LVTTL levels).
63 VDDO_F power_in QF output supply pin (LVCMOS/LVTTL), 3.3 V.
64 QF output Single-ended output, 3.3 V LVCMOS/LVTTL interface levels.
65 VDDO_G power_in QG output supply pin (LVCMOS/LVTTL), 3.3 V or 2.5 V.
66 QG output Single-ended output, 3.3 V or 2.5 V LVCMOS/LVTTL interface levels.
67 OE_G input Active HIGH output enable for the QG output (pullup); LOW puts QG in high impedance.
68 OE_REF input Active HIGH output enable for QREF[0:1] outputs (pullup); LOW puts QREF outputs in high impedance.
69 QREF0 output Single-ended REF output, 3.3 V or 2.5 V LVCMOS/LVTTL interface levels.
70 QREF1 output Single-ended REF output, 3.3 V or 2.5 V LVCMOS/LVTTL interface levels.
71 VDDO_QREF power_in QREF[0:1] output supply pin (LVCMOS/LVTTL), 3.3 V or 2.5 V.
72 nc unconnected No connect.
73 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package QFN-72-EP(10x10)
Category Clock and Timing
Pins 73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Core Supply Voltage VDD 3.135 3.3 3.465 V VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_[F:G] = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C 6
Output Supply Voltage VDDO_X 3.135 3.3 3.465 V VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_[F:G] = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C 6
Power Supply Current IDD 86 103 mA VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_[F:G] = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C 6
Analog Supply Current IDDA 13 16 mA VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_[F:G] = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C 6
Output Supply Current IDDO_X 76 91 mA No Load, CLK selected; VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_[F:G] = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C 6
Output Supply Voltage VDDO_X 2.375 2.5 2.625 V VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C 6
Power Supply Current IDD 79 95 mA VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C 6
Output Supply Current IDDO_X 50 60 mA No Load, CLK selected; VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C 6
Input High Voltage VIH 2.2 V VDD = VDDO_F = 3.3V ± 5%; or VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C (max printed as VDD + 0.3) 7
Input Low Voltage VIL -0.3 0.8 V VDD = VDDO_F = 3.3V ± 5%; or VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C 7
Input High Current (FSEL pins) IIH 150 µA FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_D[0:1], FSEL_E[0:1]; VDD = VIN = 3.465V 7
Input High Current (nMR, REF_SEL, PLL_SEL, OE pins) IIH 10 uA nMR, REF_SEL, PLL_SEL, OE_REF, OE_A, OE_B, OE_C, OE_D, OE_E, OE_G; VDD = VIN = 3.465V 7
Input Low Current (FSEL pins) IIL -10 µA FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_D[0:1], FSEL_E[0:1]; VDD = 3.465V, VIN = 0V 7
Input Low Current (nMR, REF_SEL, PLL_SEL, OE pins) IIL -150 uA nMR, REF_SEL, PLL_SEL, OE_REF, OE_A, OE_B, OE_C, OE_D, OE_E, OE_G; VDD = 3.465V, VIN = 0V 7
Output High Voltage VOH 2.6 V VDDO_F = VDDO_G, VDDO_QREF = 3.465V, IOH = -12mA 7
Output High Voltage VOH 1.8 V VDDO_G, VDDO_QREF = 2.625V, IOH = -12mA 7
Output Low Voltage VOL 0.6 V VDDO_F = VDDO_G, VDDO_QREF = 3.465V or VDDO_G, VDDO_QREF = 2.625V, IOH = 12mA 7
Input High Current (CLK, nCLK) IIH 150 µA CLK, nCLK; VDD = VIN = 3.465V 7
Input Low Current (CLK) IIL -10 µA CLK; VDD = 3.465V, VIN = 0V 7
Input Low Current (nCLK) IIL -150 µA nCLK; VDD = 3.465V, VIN = 0V 7
Peak-to-Peak Input Voltage VPP 0.15 1.3 V NOTE 1 7
Common Mode Input Voltage VCMR 0.5 V NOTE 1, 2 (max printed as VDD, 0.85) 7
Ring-Back Voltage Margin VRB -100 100 mV Q[A:E], nQ[A:E]; NOTE 1, 2 12
Time before VRB is allowed tSTABLE 500 ps Q[A:E], nQ[A:E]; NOTE 1, 2 12
Absolute Max Output Voltage VMAX 1150 mV Q[A:E], nQ[A:E]; NOTE 3, 4 12
Absolute Min Output Voltage VMIN -300 mV Q[A:E], nQ[A:E]; NOTE 3, 5 12
Absolute Crossing Voltage VCROSS 250 550 mV Q[A:E], nQ[A:E]; NOTE 3, 6, 7 12
Total Variation of VCROSS over All Edges VCROSS 140 mV Q[A:E], nQ[A:E]; NOTE 3, 6, 8 12
Rising Edge Rate tSLEW+ 0.6 5.5 V/ns Q[A:E], nQ[A:E]; NOTE 1, 9 12
Falling Edge Rate tSLEW- 0.6 5.5 V/ns Q[A:E], nQ[A:E]; NOTE 1, 9 12
Output Duty Cycle odc 48 52 % Q[A:E], nQ[A:E] 12
RMS Phase Jitter (Random) tjit(Ø) 0.6 0.96 ps QREF[0:1] 25MHz, Integration Range (10kHz to 5MHz) 12
Output Rise/Fall Time QF tR /tF 400 1400 ps QF 20% to 80% 12
Output Rise/Fall Time QG tR /tF 400 1400 ps QG 20% to 80% 12
Output Rise/Fall Time QREF tR /tF 300 1400 ps QREF[0:1] 20% to 80% 12
Output Duty Cycle QF odc 48 50 52 % QF measured at VDDO_F/2 12
Output Duty Cycle QG odc 45 50 55 % QG measured at VDDO_G/2 12
Output Duty Cycle QREF odc 45 50 55 % QREF[0:1] measured at VDDO_QREF/2 12
PCIe Phase Jitter Peak-to-Peak (Gen 1) tj 14.27 24.35 86 ps f = 100MHz, 25MHz Crystal Input; Evaluation Band: 0Hz - Nyquist 8
PCIe Phase Jitter RMS High Band (Gen 2) tREFCLK_HF_RMS 1.47 3.04 3.1 ps f = 100MHz, 25MHz Crystal Input; High Band: 1.5MHz - Nyquist 8
PCIe Phase Jitter RMS Low Band (Gen 2) tREFCLK_LF_RMS 0.17 0.67 3 ps f = 100MHz, 25MHz Crystal Input; Low Band: 10kHz - 1.5MHz 8
PCIe Phase Jitter RMS (Gen 3) tREFCLK_RMS 0.37 0.79 0.8 ps f = 100MHz, 25MHz Crystal Input; Evaluation Band: 0Hz - Nyquist 8
Total Phase Jitter RMS (sRIO) JCLK_REF 0.64 1.55 3 ps f = 125MHz, 25MHz Crystal Input, HCSL Output Clocks 8
RMS Phase Jitter (Random) QA tjit(Ø) 0.77 0.96 ps QA = QD = 100MHz, QB = QG = 125MHz, QC = QE = 156.25MHz, QF = 50MHz, QREF0 = QREF1 = Disabled; 12kHz to 20MHz 10
RMS Phase Jitter (Random) QB tjit(Ø) 0.75 0.94 ps QA = QD = 100MHz, QB = QG = 125MHz, QC = QE = 156.25MHz, QF = 50MHz, QREF0 = QREF1 = Disabled; 12kHz to 20MHz 10
RMS Phase Jitter (Random) QC tjit(Ø) 0.75 1 ps QA = QD = 100MHz, QB = QG = 125MHz, QC = QE = 156.25MHz, QF = 50MHz, QREF0 = QREF1 = Disabled; 12kHz to 20MHz 10
RMS Phase Jitter (Random) QD tjit(Ø) 0.78 0.96 ps QA = QD = 100MHz, QB = QG = 125MHz, QC = QE = 156.25MHz, QF = 50MHz, QREF0 = QREF1 = Disabled; 12kHz to 20MHz 10
RMS Phase Jitter (Random) QE tjit(Ø) 0.76 0.95 ps QA = QD = 100MHz, QB = QG = 125MHz, QC = QE = 156.25MHz, QF = 50MHz, QREF0 = QREF1 = Disabled; 12kHz to 20MHz 10
RMS Phase Jitter (Random) QF tjit(Ø) 0.94 1.09 ps QA = QD = 100MHz, QB = QG = 125MHz, QC = QE = 156.25MHz, QF = 50MHz, QREF0 = QREF1 = Disabled; 12kHz to 20MHz 10
RMS Phase Jitter (Random) QG tjit(Ø) 0.88 1.13 ps QA = QD = 100MHz, QB = QG = 125MHz, QC = QE = 156.25MHz, QF = 50MHz, QREF0 = QREF1 = Disabled; 12kHz to 20MHz 10
Absolute Supply Voltage VDD 4.6 V Rating 6
Input Voltage XTAL_IN VI 0 V XTAL_IN; 0V to VDD (max printed as VDD) 6
Input Voltage Other Inputs VI -0.5 V Other Inputs; -0.5V to VDD + 0.5V (max printed as VDD + 0.5) 6
Output Voltage VO -0.5 V Outputs; -0.5V to VDD + 0.5V (max printed as VDD + 0.5) 6
Storage Temperature TSTG -65 150 C Storage 6
Ambient Operating Temperature -40 85 °C -40°C to 85°C ambient operating temperature (Features) 1
Package Thermal Impedance JA 25.4 °C/W 0 mps (as printed) 6

CAD (KiCad official)

  • Symbol: 8413S12BKILF
  • Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • 3D model: QFN-72-EP(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 8413s12bkilf-etched.step / 8413s12bkilf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 8413s12bkilf.step / 8413s12bkilf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (34 pp, sha256 f5f33d24430b1859, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF