78L05U
Public Made by Adomby adom
CBI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-89-3. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗PCB Footprint
Open full view ↗Datasheet
Open in new tab ↗Contents
README
markdown78L05U
CBI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89-3
78L05U from CBI, in a SOT-89-3. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VO | power_out | Regulated +5 V output. Typical 5.0 V (4.75 V to 5.25 V) over 7 V ≤ VI ≤ 20 V and 1 mA ≤ IO ≤ 40 mA. Bypass with a 0.1 µF ceramic capacitor to GND close to the pin for stability. |
| 2 | GND | power_in | Common ground reference for both input and output. In the SOT-89 package this pin is also the thermal tab, so its PCB copper acts as the primary heatsink for Ptot up to 800 mW. |
| 3 | VI | power_in | Unregulated positive input supply, 7 V to 20 V for spec compliance (30 V absolute max). Bypass with a 0.33 µF capacitor to GND close to the pin to ensure loop stability and reject line transients. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CBI |
| Package | SOT-89-3 |
| Category | PMIC |
| Pins | 3 |
Ordering variants
78L05UU
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage | VO | 4.8 | 5 | 5.2 | V | Tj = 25 °C | 1 |
| Output Voltage | VO | 4.75 | 5.25 | V | 7 V ≤ VI ≤ 20 V, 1 mA ≤ IO ≤ 40 mA | 1 | |
| Line Regulation | Regline | 150 | mV | 7 V ≤ VI ≤ 20 V, Tj = 25 °C | 1 | ||
| Line Regulation | Regline | 100 | mV | 8 V ≤ VI ≤ 20 V, Tj = 25 °C | 1 | ||
| Load Regulation | Regload | 60 | mV | 1 mA ≤ IO ≤ 100 mA, Tj = 25 °C | 1 | ||
| Load Regulation | Regload | 30 | mV | 1 mA ≤ IO ≤ 40 mA, Tj = 25 °C | 1 | ||
| Quiescent Current | IQ | 5.5 | mA | Tj = 25 °C | 1 | ||
| Quiescent Current Change | ΔIQ | 1.5 | mA | 8 V ≤ VI ≤ 20 V | 1 | ||
| Quiescent Current Change | ΔIQ | 0.1 | mA | 1 mA ≤ IO ≤ 40 mA | 1 | ||
| Ripple Rejection | RR | 41 | dB | f = 120 Hz, 8 V ≤ VI ≤ 18 V, Tj = 25 °C | 1 | ||
| Input Voltage | VI | 30 | V | 1 | |||
| Power Dissipation | Ptot | 800 | mW | 15 mm X 25 mm X 0.7 mm alumina ceramic board, Ta ≤ 25 °C (footnote 1) | 1 | ||
| Operating Temperature | Topr | -20 | 120 | °C | 1 | ||
| Storage Temperature Range | Tstg | -55 | 150 | °C | 1 |
CAD (KiCad official)
- Symbol:
78L05U - Footprint:
Package_TO_SOT_SMD:SOT-89-3 - 3D model: SOT-89-3 (KiCad packages3D, STEP)
- 3D model files:
78l05u-etched.step/78l05u-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);78l05u.step/78l05u.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
78l05u.step |
57 KB | You want the bare part, or you mark your own boards. |
78l05u-etched.step |
1.0 MB | You want the part with 78L05U already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 282 faces against 42 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CBI datasheet (2 pp, sha256
051ac44ab6bfa721, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).