component
74VHCT573AFT
Public Made by Adomby adom
TOSHIBA Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74VHCT573AFT
TOSHIBA · Logic ICs · TSSOP-20
74VHCT573AFT from TOSHIBA, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable input; when high the eight outputs are in a high-impedance state. |
| 2 | D0 | input | Data input 0 of the octal D-type latch. |
| 3 | D1 | input | Data input 1 of the octal D-type latch. |
| 4 | D2 | input | Data input 2 of the octal D-type latch. |
| 5 | D3 | input | Data input 3 of the octal D-type latch. |
| 6 | D4 | input | Data input 4 of the octal D-type latch. |
| 7 | D5 | input | Data input 5 of the octal D-type latch. |
| 8 | D6 | input | Data input 6 of the octal D-type latch. |
| 9 | D7 | input | Data input 7 of the octal D-type latch. |
| 10 | GND | power_in | Ground, 0 V reference. |
| 11 | LE | input | Latch enable input; Q outputs are latched when LE goes low. |
| 12 | Q7 | tri_state | 3-state latch output 7; high impedance when OE is high. |
| 13 | Q6 | tri_state | 3-state latch output 6; high impedance when OE is high. |
| 14 | Q5 | tri_state | 3-state latch output 5; high impedance when OE is high. |
| 15 | Q4 | tri_state | 3-state latch output 4; high impedance when OE is high. |
| 16 | Q3 | tri_state | 3-state latch output 3; high impedance when OE is high. |
| 17 | Q2 | tri_state | 3-state latch output 2; high impedance when OE is high. |
| 18 | Q1 | tri_state | 3-state latch output 1; high impedance when OE is high. |
| 19 | Q0 | tri_state | 3-state latch output 0; high impedance when OE is high. |
| 20 | VCC | power_in | Positive supply voltage, operating range 4.5 to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | TSSOP-20 |
| Category | Logic ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input voltage | VIN | -0.5 | 7 | V | 4 | ||
| Output voltage | VOUT | -0.5 | 7 | V | Output in off-state (Note 1) | 4 | |
| Input diode current | IIK | -20 | mA | 4 | |||
| Output diode current | IOK | -20 | 20 | mA | 4 | ||
| Output current | IOUT | -25 | 25 | mA | 4 | ||
| VCC/ground current | ICC | -75 | 75 | mA | 4 | ||
| Power dissipation | PD | 180 | mW | Ta = -40 to 85 °C (Note 4) | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 4.5 | 5.5 | V | 4 | ||
| Input voltage | VIN | 0 | 5.5 | V | 4 | ||
| Output voltage | VOUT | 0 | 5.5 | V | Output in off-state (Note 1) | 4 | |
| Output voltage | VOUT | 0 | V | High or low state (Note 2); printed upper limit is VCC | 4 | ||
| Operating temperature | Topr | -40 | 125 | °C | 4 | ||
| Input rise and fall times | dt/dv | 0 | 20 | ns/V | 4 | ||
| High-level input voltage | VIH | 2 | V | Ta = 25 °C | 5 | ||
| Low-level input voltage | VIL | 0.8 | V | Ta = 25 °C | 5 | ||
| High-level output voltage | VOH | 4.4 | 4.5 | V | Ta = 25 °C; VIN = VIH or VIL; IOH = -50 µA | 5 | |
| High-level output voltage | VOH | 3.94 | V | Ta = 25 °C; VIN = VIH or VIL; IOH = -8 mA | 5 | ||
| Low-level output voltage | VOL | 0 | 0.1 | V | Ta = 25 °C; VIN = VIH or VIL; IOL = 50 µA | 5 | |
| Low-level output voltage | VOL | 0.36 | V | Ta = 25 °C; VIN = VIH or VIL; IOL = 8 mA | 5 | ||
| 3-state output OFF-state leakage current | IOZ | -0.25 | 0.25 | µA | Ta = 25 °C; VOUT = VCC or GND | 5 | |
| Input leakage current | IIN | -0.1 | 0.1 | µA | Ta = 25 °C; VIN = 5.5 V or GND | 5 | |
| Quiescent supply current | ICC | 4 | µA | Ta = 25 °C; VIN = VCC or GND | 5 | ||
| Quiescent supply current (per input, ΔICC) | ICCT | 1.35 | mA | Ta = 25 °C; per input VIN = 3.4 V; other input VCC or GND | 5 | ||
| Output leakage current (Power-OFF) | IOPD | 0.5 | µA | Ta = 25 °C; VOUT = 5.5 V | 5 | ||
| High-level output voltage | VOH | 4.4 | V | Ta = -40 to 85 °C; VIN = VIH or VIL; IOH = -50 µA | 5 | ||
| High-level output voltage | VOH | 3.8 | V | Ta = -40 to 85 °C; VIN = VIH or VIL; IOH = -8 mA | 5 | ||
| Low-level output voltage | VOL | 0.1 | V | Ta = -40 to 85 °C; VIN = VIH or VIL; IOL = 50 µA | 5 | ||
| Low-level output voltage | VOL | 0.44 | V | Ta = -40 to 85 °C; VIN = VIH or VIL; IOL = 8 mA | 5 | ||
| 3-state output OFF-state leakage current | IOZ | -2.5 | 2.5 | µA | Ta = -40 to 85 °C; VOUT = VCC or GND | 5 | |
| Input leakage current | IIN | -1 | 1 | µA | Ta = -40 to 85 °C; VIN = 5.5 V or GND | 5 | |
| Quiescent supply current | ICC | 40 | µA | Ta = -40 to 85 °C; VIN = VCC or GND | 5 | ||
| Quiescent supply current (per input, ΔICC) | ICCT | 1.5 | mA | Ta = -40 to 85 °C; per input VIN = 3.4 V; other input VCC or GND | 5 | ||
| Output leakage current (Power-OFF) | IOPD | 5 | µA | Ta = -40 to 85 °C; VOUT = 5.5 V | 5 | ||
| High-level output voltage | VOH | 3.7 | V | Ta = -40 to 125 °C; VIN = VIH or VIL; IOH = -8 mA | 5 | ||
| Low-level output voltage | VOL | 0.55 | V | Ta = -40 to 125 °C; VIN = VIH or VIL; IOL = 8 mA | 5 | ||
| 3-state output OFF-state leakage current | IOZ | -10 | 10 | µA | Ta = -40 to 125 °C; VOUT = VCC or GND | 5 | |
| Input leakage current | IIN | -2 | 2 | µA | Ta = -40 to 125 °C; VIN = 5.5 V or GND | 5 | |
| Quiescent supply current | ICC | 80 | µA | Ta = -40 to 125 °C; VIN = VCC or GND | 5 | ||
| Output leakage current (Power-OFF) | IOPD | 20 | µA | Ta = -40 to 125 °C; VOUT = 5.5 V | 5 | ||
| Minimum pulse width (LE) | tw(H) | 8.5 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; tr = tf = 3 ns | 6 | ||
| Minimum setup time | tSth | 2 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; tr = tf = 3 ns | 6 | ||
| Minimum hold time | tSth | 3.5 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; tr = tf = 3 ns | 6 | ||
| Propagation delay time (LE-Q) | tPLH,tPHL | 1 | 15.5 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 | |
| Propagation delay time (LE-Q) | tPLH,tPHL | 1 | 17 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 | |
| Propagation delay time (D-Q) | tPLH,tPHL | 1 | 11 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 | |
| Propagation delay time (D-Q) | tPLH,tPHL | 1 | 12 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 | |
| 3-state output enable time | tPZL,tPZH | 1 | 14 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 | |
| 3-state output enable time | tPZL,tPZH | 1 | 15 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 | |
| 3-state output disable time | tPLZ,tPHZ | 1 | 14 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 | |
| Output skew | tosLH,tosHL | 1 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; tr = tf = 3 ns | 7 | ||
| Input capacitance | CIN | 10 | pF | Ta = -40 to 125 °C; tr = tf = 3 ns | 7 |
CAD (KiCad official)
- Symbol:
74VHCT573AFT - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74vhct573aft-etched.step/74vhct573aft-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74vhct573aft.step/74vhct573aft.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (9 pp, sha256
d44860dec53588dd, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74VHCT573AFT
**TOSHIBA** · Logic ICs · TSSOP-20
74VHCT573AFT from TOSHIBA, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable input; when high the eight outputs are in a high-impedance state. |
| 2 | D0 | input | Data input 0 of the octal D-type latch. |
| 3 | D1 | input | Data input 1 of the octal D-type latch. |
| 4 | D2 | input | Data input 2 of the octal D-type latch. |
| 5 | D3 | input | Data input 3 of the octal D-type latch. |
| 6 | D4 | input | Data input 4 of the octal D-type latch. |
| 7 | D5 | input | Data input 5 of the octal D-type latch. |
| 8 | D6 | input | Data input 6 of the octal D-type latch. |
| 9 | D7 | input | Data input 7 of the octal D-type latch. |
| 10 | GND | power_in | Ground, 0 V reference. |
| 11 | LE | input | Latch enable input; Q outputs are latched when LE goes low. |
| 12 | Q7 | tri_state | 3-state latch output 7; high impedance when OE is high. |
| 13 | Q6 | tri_state | 3-state latch output 6; high impedance when OE is high. |
| 14 | Q5 | tri_state | 3-state latch output 5; high impedance when OE is high. |
| 15 | Q4 | tri_state | 3-state latch output 4; high impedance when OE is high. |
| 16 | Q3 | tri_state | 3-state latch output 3; high impedance when OE is high. |
| 17 | Q2 | tri_state | 3-state latch output 2; high impedance when OE is high. |
| 18 | Q1 | tri_state | 3-state latch output 1; high impedance when OE is high. |
| 19 | Q0 | tri_state | 3-state latch output 0; high impedance when OE is high. |
| 20 | VCC | power_in | Positive supply voltage, operating range 4.5 to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | TSSOP-20 |
| Category | Logic ICs |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| Input voltage | VIN | -0.5 | | 7 | V | | 4 |
| Output voltage | VOUT | -0.5 | | 7 | V | Output in off-state (Note 1) | 4 |
| Input diode current | IIK | -20 | | | mA | | 4 |
| Output diode current | IOK | -20 | | 20 | mA | | 4 |
| Output current | IOUT | -25 | | 25 | mA | | 4 |
| VCC/ground current | ICC | -75 | | 75 | mA | | 4 |
| Power dissipation | PD | | | 180 | mW | Ta = -40 to 85 °C (Note 4) | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Supply voltage | VCC | 4.5 | | 5.5 | V | | 4 |
| Input voltage | VIN | 0 | | 5.5 | V | | 4 |
| Output voltage | VOUT | 0 | | 5.5 | V | Output in off-state (Note 1) | 4 |
| Output voltage | VOUT | 0 | | | V | High or low state (Note 2); printed upper limit is VCC | 4 |
| Operating temperature | Topr | -40 | | 125 | °C | | 4 |
| Input rise and fall times | dt/dv | 0 | | 20 | ns/V | | 4 |
| High-level input voltage | VIH | 2 | | | V | Ta = 25 °C | 5 |
| Low-level input voltage | VIL | | | 0.8 | V | Ta = 25 °C | 5 |
| High-level output voltage | VOH | 4.4 | 4.5 | | V | Ta = 25 °C; VIN = VIH or VIL; IOH = -50 µA | 5 |
| High-level output voltage | VOH | 3.94 | | | V | Ta = 25 °C; VIN = VIH or VIL; IOH = -8 mA | 5 |
| Low-level output voltage | VOL | | 0 | 0.1 | V | Ta = 25 °C; VIN = VIH or VIL; IOL = 50 µA | 5 |
| Low-level output voltage | VOL | | | 0.36 | V | Ta = 25 °C; VIN = VIH or VIL; IOL = 8 mA | 5 |
| 3-state output OFF-state leakage current | IOZ | -0.25 | | 0.25 | µA | Ta = 25 °C; VOUT = VCC or GND | 5 |
| Input leakage current | IIN | -0.1 | | 0.1 | µA | Ta = 25 °C; VIN = 5.5 V or GND | 5 |
| Quiescent supply current | ICC | | | 4 | µA | Ta = 25 °C; VIN = VCC or GND | 5 |
| Quiescent supply current (per input, ΔICC) | ICCT | | | 1.35 | mA | Ta = 25 °C; per input VIN = 3.4 V; other input VCC or GND | 5 |
| Output leakage current (Power-OFF) | IOPD | | | 0.5 | µA | Ta = 25 °C; VOUT = 5.5 V | 5 |
| High-level output voltage | VOH | 4.4 | | | V | Ta = -40 to 85 °C; VIN = VIH or VIL; IOH = -50 µA | 5 |
| High-level output voltage | VOH | 3.8 | | | V | Ta = -40 to 85 °C; VIN = VIH or VIL; IOH = -8 mA | 5 |
| Low-level output voltage | VOL | | | 0.1 | V | Ta = -40 to 85 °C; VIN = VIH or VIL; IOL = 50 µA | 5 |
| Low-level output voltage | VOL | | | 0.44 | V | Ta = -40 to 85 °C; VIN = VIH or VIL; IOL = 8 mA | 5 |
| 3-state output OFF-state leakage current | IOZ | -2.5 | | 2.5 | µA | Ta = -40 to 85 °C; VOUT = VCC or GND | 5 |
| Input leakage current | IIN | -1 | | 1 | µA | Ta = -40 to 85 °C; VIN = 5.5 V or GND | 5 |
| Quiescent supply current | ICC | | | 40 | µA | Ta = -40 to 85 °C; VIN = VCC or GND | 5 |
| Quiescent supply current (per input, ΔICC) | ICCT | | | 1.5 | mA | Ta = -40 to 85 °C; per input VIN = 3.4 V; other input VCC or GND | 5 |
| Output leakage current (Power-OFF) | IOPD | | | 5 | µA | Ta = -40 to 85 °C; VOUT = 5.5 V | 5 |
| High-level output voltage | VOH | 3.7 | | | V | Ta = -40 to 125 °C; VIN = VIH or VIL; IOH = -8 mA | 5 |
| Low-level output voltage | VOL | | | 0.55 | V | Ta = -40 to 125 °C; VIN = VIH or VIL; IOL = 8 mA | 5 |
| 3-state output OFF-state leakage current | IOZ | -10 | | 10 | µA | Ta = -40 to 125 °C; VOUT = VCC or GND | 5 |
| Input leakage current | IIN | -2 | | 2 | µA | Ta = -40 to 125 °C; VIN = 5.5 V or GND | 5 |
| Quiescent supply current | ICC | | | 80 | µA | Ta = -40 to 125 °C; VIN = VCC or GND | 5 |
| Output leakage current (Power-OFF) | IOPD | | | 20 | µA | Ta = -40 to 125 °C; VOUT = 5.5 V | 5 |
| Minimum pulse width (LE) | tw(H) | 8.5 | | | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; tr = tf = 3 ns | 6 |
| Minimum setup time | tSth | 2 | | | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; tr = tf = 3 ns | 6 |
| Minimum hold time | tSth | 3.5 | | | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; tr = tf = 3 ns | 6 |
| Propagation delay time (LE-Q) | tPLH,tPHL | 1 | | 15.5 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 |
| Propagation delay time (LE-Q) | tPLH,tPHL | 1 | | 17 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 |
| Propagation delay time (D-Q) | tPLH,tPHL | 1 | | 11 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 |
| Propagation delay time (D-Q) | tPLH,tPHL | 1 | | 12 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 |
| 3-state output enable time | tPZL,tPZH | 1 | | 14 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 |
| 3-state output enable time | tPZL,tPZH | 1 | | 15 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 |
| 3-state output disable time | tPLZ,tPHZ | 1 | | 14 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; RL = 1 kΩ; tr = tf = 3 ns | 7 |
| Output skew | tosLH,tosHL | | | 1 | ns | Ta = -40 to 125 °C; VCC = 5.0 ± 0.5 V; CL = 50 pF; tr = tf = 3 ns | 7 |
| Input capacitance | CIN | | | 10 | pF | Ta = -40 to 125 °C; tr = tf = 3 ns | 7 |
## CAD (KiCad official)
- Symbol: `74VHCT573AFT`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `74vhct573aft-etched.step` / `74vhct573aft-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74vhct573aft.step` / `74vhct573aft.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TOSHIBA datasheet](docs/74vhct573aft-datasheet.pdf) (9 pp, sha256 `d44860dec53588dd`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74vhct573aft-datasheet.pdf)