component
74VHCT541PW
Public Made by Adomby adom
Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
74VHCT541PW
Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
74VHCT541PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE0 | input | Output enable input (active LOW) for outputs Y0 to Y3; a HIGH on OE0 (together with OE1 HIGH) forces the outputs to the high-impedance OFF-state. |
| 2 | A0 | input | Data input 0 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 3 | A1 | input | Data input 1 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 4 | A2 | input | Data input 2 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 5 | A3 | input | Data input 3 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 6 | A4 | input | Data input 4 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 7 | A5 | input | Data input 5 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 8 | A6 | input | Data input 6 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 9 | A7 | input | Data input 7 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages in the device. |
| 11 | Y7 | tri_state | Data output 7 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 12 | Y6 | tri_state | Data output 6 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 13 | Y5 | tri_state | Data output 5 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 14 | Y4 | tri_state | Data output 4 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 15 | Y3 | tri_state | Data output 3 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 16 | Y2 | tri_state | Data output 2 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 17 | Y1 | tri_state | Data output 1 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 18 | Y0 | tri_state | Data output 0 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 19 | OE1 | input | Output enable input (active LOW) for outputs Y4 to Y7; a HIGH on OE1 (together with OE0 HIGH) forces the outputs to the high-impedance OFF-state. |
| 20 | VCC | power_in | Supply voltage; recommended 4.5 V to 5.5 V for the 74VHCT541. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input voltage | VI | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | mA | VI < -0.5 V [1] | 4 | ||
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 4 | |
| output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 | |
| supply current | ICC | 75 | mA | 4 | |||
| ground current | IGND | -75 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C [2] | 4 | ||
| supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| input voltage | VI | 0 | 5.5 | V | 4 | ||
| output voltage | VO | 0 | V | 4 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V | 6 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V | 6 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA | 6 | |
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA | 6 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA | 6 | |
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA | 6 | ||
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V | 6 | |
| input leakage current | II | 2 | μA | VI = VCC or GND; VCC = 0 V to 5.5 V | 6 | ||
| supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 6 | ||
| additional supply current | ΔICC | 1.5 | mA | per input pin; VI = VCC - 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V | 6 | ||
| input capacitance | CI | 3 | 10 | pF | 6 | ||
| propagation delay | tpd | 1 | 3.5 | 7 | ns | An to Yn; see Fig. 3; VCC = 4.5 V to 5.5 V; CL = 15 pF | 8 |
| propagation delay | tpd | 1 | 5 | 11 | ns | An to Yn; see Fig. 3; VCC = 4.5 V to 5.5 V; CL = 50 pF | 8 |
| enable time | ten | 1 | 4 | 9 | ns | OEn to Yn; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 15 pF | 8 |
| enable time | ten | 1 | 5.5 | 12.5 | ns | OEn to Yn; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 50 pF | 8 |
| disable time | tdis | 1 | 5 | 9 | ns | OEn to Yn; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 15 pF | 8 |
| disable time | tdis | 1 | 7 | 12.5 | ns | OEn to Yn; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 50 pF | 8 |
CAD (KiCad official)
- Symbol:
74VHCT541PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74vhct541pw-etched.step/74vhct541pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74vhct541pw.step/74vhct541pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
996dee2efa342abf, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74VHCT541PW
**Nexperia** · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
74VHCT541PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE0 | input | Output enable input (active LOW) for outputs Y0 to Y3; a HIGH on OE0 (together with OE1 HIGH) forces the outputs to the high-impedance OFF-state. |
| 2 | A0 | input | Data input 0 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 3 | A1 | input | Data input 1 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 4 | A2 | input | Data input 2 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 5 | A3 | input | Data input 3 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 6 | A4 | input | Data input 4 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 7 | A5 | input | Data input 5 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 8 | A6 | input | Data input 6 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 9 | A7 | input | Data input 7 with Schmitt-trigger action, accepting voltages up to 5.5 V (recommended VI 0 to 5.5 V) and higher than VCC. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages in the device. |
| 11 | Y7 | tri_state | Data output 7 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 12 | Y6 | tri_state | Data output 6 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 13 | Y5 | tri_state | Data output 5 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 14 | Y4 | tri_state | Data output 4 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 15 | Y3 | tri_state | Data output 3 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 16 | Y2 | tri_state | Data output 2 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 17 | Y1 | tri_state | Data output 1 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 18 | Y0 | tri_state | Data output 0 of the 3-state bus-compatible buffer, high-impedance when OE0 or OE1 is HIGH as per the functional table. |
| 19 | OE1 | input | Output enable input (active LOW) for outputs Y4 to Y7; a HIGH on OE1 (together with OE0 HIGH) forces the outputs to the high-impedance OFF-state. |
| 20 | VCC | power_in | Supply voltage; recommended 4.5 V to 5.5 V for the 74VHCT541. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| input voltage | VI | -0.5 | | 7 | V | | 4 |
| input clamping current | IIK | -20 | | | mA | VI < -0.5 V [1] | 4 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 4 |
| output current | IO | -25 | | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 |
| supply current | ICC | | | 75 | mA | | 4 |
| ground current | IGND | -75 | | | mA | | 4 |
| storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C [2] | 4 |
| supply voltage | VCC | 4.5 | 5 | 5.5 | V | | 4 |
| input voltage | VI | 0 | | 5.5 | V | | 4 |
| output voltage | VO | 0 | | | V | | 4 |
| ambient temperature | Tamb | -40 | 25 | 125 | °C | | 4 |
| input transition rise and fall rate | Δt/ΔV | | | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 4 |
| HIGH-level input voltage | VIH | 2 | | | V | VCC = 4.5 V to 5.5 V | 6 |
| LOW-level input voltage | VIL | | | 0.8 | V | VCC = 4.5 V to 5.5 V | 6 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA | 6 |
| HIGH-level output voltage | VOH | 3.7 | | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA | 6 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA | 6 |
| LOW-level output voltage | VOL | | | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA | 6 |
| OFF-state output current | IOZ | -10 | | 10 | μA | VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V | 6 |
| input leakage current | II | | | 2 | μA | VI = VCC or GND; VCC = 0 V to 5.5 V | 6 |
| supply current | ICC | | | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 6 |
| additional supply current | ΔICC | | | 1.5 | mA | per input pin; VI = VCC - 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V | 6 |
| input capacitance | CI | | 3 | 10 | pF | | 6 |
| propagation delay | tpd | 1 | 3.5 | 7 | ns | An to Yn; see Fig. 3; VCC = 4.5 V to 5.5 V; CL = 15 pF | 8 |
| propagation delay | tpd | 1 | 5 | 11 | ns | An to Yn; see Fig. 3; VCC = 4.5 V to 5.5 V; CL = 50 pF | 8 |
| enable time | ten | 1 | 4 | 9 | ns | OEn to Yn; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 15 pF | 8 |
| enable time | ten | 1 | 5.5 | 12.5 | ns | OEn to Yn; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 50 pF | 8 |
| disable time | tdis | 1 | 5 | 9 | ns | OEn to Yn; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 15 pF | 8 |
| disable time | tdis | 1 | 7 | 12.5 | ns | OEn to Yn; see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 50 pF | 8 |
## CAD (KiCad official)
- Symbol: `74VHCT541PW`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `74vhct541pw-etched.step` / `74vhct541pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74vhct541pw.step` / `74vhct541pw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74VHCT541PW.pdf) (16 pp, sha256 `996dee2efa342abf`, retrieved 2026-10-21, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74vhct541pw-datasheet.pdf)