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74VHCT240AFT

TOSHIBA · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

74VHCT240AFT from TOSHIBA, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1G input Active-low 3-state output enable for the first buffer group (1A1-1A4 to 1Y1-1Y4); inputs 0 to 5.5 V, VIH 2.0 V min, VIL 0.8 V max.
2 1A1 input Data input 1A1 of group 1, inverted to output 1Y1; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max.
3 2Y4 tri_state Inverting 3-state output of group 2 driven from 2A4; high impedance when 2G is high.
4 1A2 input Data input 1A2 of group 1, inverted to output 1Y2; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max.
5 2Y3 tri_state Inverting 3-state output of group 2 driven from 2A3; high impedance when 2G is high.
6 1A3 input Data input 1A3 of group 1, inverted to output 1Y3; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max.
7 2Y2 tri_state Inverting 3-state output of group 2 driven from 2A2; high impedance when 2G is high.
8 1A4 input Data input 1A4 of group 1, inverted to output 1Y4; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max.
9 2Y1 tri_state Inverting 3-state output of group 2 driven from 2A1; high impedance when 2G is high.
10 GND power_in Ground pin (0 V).
11 2A1 input Data input 2A1 of group 2, inverted to output 2Y1; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max.
12 1Y4 tri_state Inverting 3-state output of group 1 driven from 1A4; high impedance when 1G is high.
13 2A2 input Data input 2A2 of group 2, inverted to output 2Y2; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max.
14 1Y3 tri_state Inverting 3-state output of group 1 driven from 1A3; high impedance when 1G is high.
15 2A3 input Data input 2A3 of group 2, inverted to output 2Y3; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max.
16 1Y2 tri_state Inverting 3-state output of group 1 driven from 1A2; high impedance when 1G is high.
17 2A4 input Data input 2A4 of group 2, inverted to output 2Y4; TTL-compatible with VIH 2.0 V min and VIL 0.8 V max.
18 1Y1 tri_state Inverting 3-state output of group 1 driven from 1A1; high impedance when 1G is high.
19 2G input Active-low 3-state output enable for the second buffer group (2A1-2A4 to 2Y1-2Y4); inputs 0 to 5.5 V, VIH 2.0 V min, VIL 0.8 V max.
20 VCC power_in Supply voltage pin, operating range 4.5 to 5.5 V.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level input voltage VIH 2 V VCC = 4.5 to 5.5 V, Ta = 25 C 5
Low-level input voltage VIL 0.8 V VCC = 4.5 to 5.5 V, Ta = 25 C 5
High-level output voltage VOH 4.4 4.5 V VIN = VIH or VIL, IOH = -50 uA, VCC = 4.5 V, Ta = 25 C 5
High-level output voltage VOH 3.94 V VIN = VIH or VIL, IOH = -8 mA, VCC = 4.5 V, Ta = 25 C 5
Low-level output voltage VOL 0 0.1 V VIN = VIH or VIL, IOL = 50 uA, VCC = 4.5 V, Ta = 25 C 5
Low-level output voltage VOL 0.36 V VIN = VIH or VIL, IOL = 8 mA, VCC = 4.5 V, Ta = 25 C 5
3-state output OFF-state leakage current IOZ -0.25 0.25 uA VIN = VIH or VIL, VOUT = VCC or GND, Ta = 25 C 5
Input leakage current IIN -0.1 0.1 uA VIN = 5.5 V or GND, Ta = 25 C 5
Quiescent supply current ICC 4 uA VIN = VCC or GND, Ta = 25 C 5
Quiescent supply current (per input) ICCT 1.35 mA Per input: VIN = 3.4 V, other input VCC or GND, Ta = 25 C 5
Output leakage current (Power-OFF) IOPD 0.5 uA VOUT = 5.5 V, Ta = 25 C 5
High-level output voltage VOH 4.4 V VIN = VIH or VIL, IOH = -50 uA, VCC = 4.5 V, Ta = -40 to 85 C 5
High-level output voltage VOH 3.8 V VIN = VIH or VIL, IOH = -8 mA, VCC = 4.5 V, Ta = -40 to 85 C 5
Low-level output voltage VOL 0.1 V VIN = VIH or VIL, IOL = 50 uA, VCC = 4.5 V, Ta = -40 to 85 C 5
Low-level output voltage VOL 0.44 V VIN = VIH or VIL, IOL = 8 mA, VCC = 4.5 V, Ta = -40 to 85 C 5
3-state output OFF-state leakage current IOZ -2.5 2.5 uA VIN = VIH or VIL, VOUT = VCC or GND, Ta = -40 to 85 C 5
Input leakage current IIN -1 1 uA VIN = 5.5 V or GND, Ta = -40 to 85 C 5
Quiescent supply current ICC 40 uA VIN = VCC or GND, Ta = -40 to 85 C 5
Quiescent supply current (per input) ICCT 1.5 mA Per input: VIN = 3.4 V, other input VCC or GND, Ta = -40 to 85 C 5
Output leakage current (Power-OFF) IOPD 5 uA VOUT = 5.5 V, Ta = -40 to 85 C 5
High-level output voltage VOH 3.7 V VIN = VIH or VIL, IOH = -8 mA, VCC = 4.5 V, Ta = -40 to 125 C 5
Low-level output voltage VOL 0.55 V VIN = VIH or VIL, IOL = 8 mA, VCC = 4.5 V, Ta = -40 to 125 C 5
3-state output OFF-state leakage current IOZ -10 10 uA VIN = VIH or VIL, VOUT = VCC or GND, Ta = -40 to 125 C 5
Input leakage current IIN -2 2 uA VIN = 5.5 V or GND, Ta = -40 to 125 C 5
Quiescent supply current ICC 80 uA VIN = VCC or GND, Ta = -40 to 125 C 5
Output leakage current (Power-OFF) IOPD 20 uA VOUT = 5.5 V, Ta = -40 to 125 C 5
Propagation delay time (74VHCT240AFT) tPLH,tPHL 5.6 7.8 ns Ta = 25 C, VCC = 5.0 +/- 0.5 V, CL = 15 pF, RL = 1 kOhm 6
Propagation delay time (74VHCT240AFT) tPLH,tPHL 6.1 8.8 ns Ta = 25 C, VCC = 5.0 +/- 0.5 V, CL = 50 pF, RL = 1 kOhm 6
Propagation delay time (74VHCT240AFT) tPLH,tPHL 1 9 ns Ta = -40 to 85 C, VCC = 5.0 +/- 0.5 V, CL = 15 pF, RL = 1 kOhm 6
Propagation delay time (74VHCT240AFT) tPLH,tPHL 1 10 ns Ta = -40 to 85 C, VCC = 5.0 +/- 0.5 V, CL = 50 pF, RL = 1 kOhm 6
Propagation delay time (74VHCT240AFT) tPLH,tPHL 1 11 ns Ta = -40 to 125 C, VCC = 5.0 +/- 0.5 V, CL = 50 pF, RL = 1 kOhm 6
Input capacitance CIN 10 pF VCC = 5.0 +/- 0.5 V, Ta = -40 to 85 C 6
Supply voltage VCC -0.5 7 V 4
Input voltage VIN -0.5 7 V 4
Output voltage VOUT -0.5 7 V Output in off-state (Note 1); VOUT < GND or VOUT > VCC (Note 3) 4
Input diode current IIK -20 mA 4
Output diode current IOK -20 20 mA 4
Output current IOUT -25 25 mA High (H) or Low (L) state (Note 2) 4
VCC/ground current ICC -75 75 mA 4
Power dissipation PD 180 mW Ta = -40 to 85 C (Note 4) 4
Storage temperature Tstg -65 150 C 4
Supply voltage VCC 4.5 5.5 V 4
Input voltage VIN 0 5.5 V 4
Output voltage VOUT 0 5.5 V Output in OFF state (Note 1) 4
Output voltage VOUT 0 V Output High or Low state (Note 2); upper limit VCC 4
Operating temperature Topr -40 125 C 4
Input rise and fall times dt/dv 0 20 ns/V 4

CAD (KiCad official)

  • Symbol: 74VHCT240AFT
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74vhct240aft-etched.step / 74vhct240aft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74vhct240aft.step / 74vhct240aft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (9 pp, sha256 3e200ea129a9f3ca, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF