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74VHCT125PW

Public Made by Adom

by adom

Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74VHCT125PW

Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-14

74VHCT125PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input for buffer 1, active LOW; a HIGH level causes 1Y to assume the high-impedance OFF-state.
2 1A input Data input for buffer 1, which drives 1Y (non-inverting).
3 1Y tri_state 3-state data output of buffer 1; high-impedance when 1OE is HIGH.
4 2OE input Output enable input for buffer 2, active LOW; a HIGH level causes 2Y to assume the high-impedance OFF-state.
5 2A input Data input for buffer 2, which drives 2Y (non-inverting).
6 2Y tri_state 3-state data output of buffer 2; high-impedance when 2OE is HIGH.
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 3Y tri_state 3-state data output of buffer 3; high-impedance when 3OE is HIGH.
9 3A input Data input for buffer 3, which drives 3Y (non-inverting).
10 3OE input Output enable input for buffer 3, active LOW; a HIGH level causes 3Y to assume the high-impedance OFF-state.
11 4Y tri_state 3-state data output of buffer 4; high-impedance when 4OE is HIGH.
12 4A input Data input for buffer 4, which drives 4Y (non-inverting).
13 4OE input Output enable input for buffer 4, active LOW; a HIGH level causes 4Y to assume the high-impedance OFF-state.
14 VCC power_in Supply voltage; the 74VHCT125 is specified for 4.5 V to 5.5 V (absolute maximum 7.0 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 3
Input voltage VI 0 5.5 V 3
Output voltage VO 0 V 3
Ambient temperature Tamb -40 25 125 °C 3
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 5.0 V ± 0.5 V 3
Supply voltage VCC -0.5 7 V 3
Input voltage VI -0.5 7 V 3
Input clamping current IIK -20 mA VI < -0.5 V 3
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 3
Supply current ICC 75 mA 3
Ground current IGND -75 mA 3
Storage temperature Tstg -65 150 °C 3
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
HIGH-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V; 25 °C 4
LOW-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V; 25 °C 4
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA; 25 °C 4
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA; -40 °C to +85 °C 4
HIGH-level output voltage VOH 3.94 V VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA; 25 °C 4
HIGH-level output voltage VOH 3.8 V VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA; -40 °C to +85 °C 4
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; VCC = 4.5 V; IO = -8.0 mA; -40 °C to +125 °C 4
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA; 25 °C 4
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA; -40 °C to +85 °C 4
LOW-level output voltage VOL 0.36 V VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; 25 °C 4
LOW-level output voltage VOL 0.44 V VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; -40 °C to +85 °C 4
LOW-level output voltage VOL 0.55 V VI = VIH or VIL; VCC = 4.5 V; IO = 8.0 mA; -40 °C to +125 °C 4
OFF-state output current IOZ -0.25 0.25 μA per input pin; VI = VIH or VIL; VCC = 5.5 V; IO = 0 A; VO = VCC or GND; other pins at VCC or GND; 25 °C 5
OFF-state output current IOZ -2.5 2.5 μA per input pin; VI = VIH or VIL; VCC = 5.5 V; IO = 0 A; VO = VCC or GND; other pins at VCC or GND; -40 °C to +85 °C 5
OFF-state output current IOZ -10 10 μA per input pin; VI = VIH or VIL; VCC = 5.5 V; IO = 0 A; VO = VCC or GND; other pins at VCC or GND; -40 °C to +125 °C 5
Input leakage current II 0.1 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V; 25 °C 5
Input leakage current II 1 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +85 °C 5
Input leakage current II 2 μA VI = 5.5 V or GND; VCC = 0 V to 5.5 V; -40 °C to +125 °C 5
Supply current ICC 2 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C 5
Supply current ICC 20 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C 5
Supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C 5
Additional supply current ΔICC 1.35 mA per input pin; VI = VCC - 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C 5
Additional supply current ΔICC 1.5 mA per input pin; VI = VCC - 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 5
Propagation delay nA to nY tpd 3 5.5 ns see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 15 pF; 25 °C 6
Propagation delay nA to nY tpd 1 6.5 ns see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +85 °C 6
Propagation delay nA to nY tpd 1 7 ns see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +125 °C 6
Propagation delay nA to nY tpd 4.3 7.5 ns see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 50 pF; 25 °C 6
Propagation delay nA to nY tpd 1 8.5 ns see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +85 °C 6
Propagation delay nA to nY tpd 1 9.5 ns see Fig. 4; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C 6
Enable time nOE to nY ten 3.4 5.1 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 15 pF; 25 °C 6
Enable time nOE to nY ten 1 6 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +85 °C 6
Enable time nOE to nY ten 1 6.5 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +125 °C 6
Enable time nOE to nY ten 4.9 7.3 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 50 pF; 25 °C 6
Enable time nOE to nY ten 1 8.3 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +85 °C 6
Enable time nOE to nY ten 1 9.5 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C 6
Disable time nOE to nY tdis 4.5 6.8 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 15 pF; 25 °C 6
Disable time nOE to nY tdis 1 8.5 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 15 pF; -40 °C to +125 °C 6
Disable time nOE to nY tdis 6.5 8.8 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 50 pF; 25 °C 6
Disable time nOE to nY tdis 1 11 ns see Fig. 5; VCC = 4.5 V to 5.5 V; CL = 50 pF; -40 °C to +125 °C 6

CAD (KiCad official)

  • Symbol: 74VHCT125PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74vhct125pw-etched.step / 74vhct125pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74vhct125pw.step / 74vhct125pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 1916966c42a73890, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF