component
74VHC595D
Public Made by Adomby adom
Nexperia Shift Registers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74VHC595D
Nexperia · Shift Registers · SO-16
74VHC595D from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | tri_state | Parallel 3-state data output of storage register stage 1; it goes to high-impedance OFF-state when OE is HIGH. |
| 2 | Q2 | tri_state | Parallel 3-state data output of storage register stage 2; it goes to high-impedance OFF-state when OE is HIGH. |
| 3 | Q3 | tri_state | Parallel 3-state data output of storage register stage 3; it goes to high-impedance OFF-state when OE is HIGH. |
| 4 | Q4 | tri_state | Parallel 3-state data output of storage register stage 4; it goes to high-impedance OFF-state when OE is HIGH. |
| 5 | Q5 | tri_state | Parallel 3-state data output of storage register stage 5; it goes to high-impedance OFF-state when OE is HIGH. |
| 6 | Q6 | tri_state | Parallel 3-state data output of storage register stage 6; it goes to high-impedance OFF-state when OE is HIGH. |
| 7 | Q7 | tri_state | Parallel 3-state data output of storage register stage 7; it goes to high-impedance OFF-state when OE is HIGH. |
| 8 | GND | power_in | Ground reference (0 V) for all voltages in the datasheet. |
| 9 | Q7S | output | Serial standard data output of the 8-stage shift register used for cascading to another device; it is not disabled by OE. |
| 10 | MR | input | Asynchronous master reset, active LOW, that clears all 8 shift register stages and affects only the shift register, not the storage register. |
| 11 | SHCP | input | Shift register clock input; data is shifted through the register on each positive-going (LOW-to-HIGH) transition. |
| 12 | STCP | input | Storage register clock input; shift register contents are transferred to the storage register and parallel outputs on its positive-going transition. |
| 13 | OE | input | Output enable input, active LOW; when HIGH, outputs Q0 to Q7 are forced to the high-impedance OFF-state. |
| 14 | DS | input | Serial data input to shift register stage 0, clocked in on the positive-going SHCP transition. |
| 15 | Q0 | tri_state | Parallel 3-state data output of storage register stage 0; it goes to high-impedance OFF-state when OE is HIGH. |
| 16 | VCC | power_in | Supply voltage; the datasheet specifies 2.0 V to 5.5 V for 74VHC595 and 4.5 V to 5.5 V for 74VHCT595 in recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| input voltage | VI | -0.5 | 7 | V | 5 | ||
| input clamping current | IIK | -20 | mA | VI < -0.5 V | 6 | ||
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 6 | |
| output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 6 | |
| supply current | ICC | 75 | mA | 6 | |||
| ground current | IGND | -75 | mA | 6 | |||
| storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 6 | ||
| supply voltage (74VHC595) | VCC | 2 | 5 | 5.5 | V | 6 | |
| input voltage | VI | 0 | 5.5 | V | 6 | ||
| output voltage | VO | 0 | V | 6 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 6 | |
| input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 3.0 V to 3.6 V | 6 | ||
| input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 4.5 V to 5.5 V | 6 | ||
| HIGH-level input voltage | VIH | 1.5 | V | -40 °C to +125 °C column; VCC = 2.0 V | 6 | ||
| HIGH-level input voltage | VIH | 2.1 | V | -40 °C to +125 °C column; VCC = 3.0 V | 6 | ||
| HIGH-level input voltage | VIH | 3.85 | V | -40 °C to +125 °C column; VCC = 5.5 V | 6 | ||
| LOW-level input voltage | VIL | 0.5 | V | -40 °C to +125 °C column; VCC = 2.0 V | 6 | ||
| LOW-level input voltage | VIL | 0.9 | V | -40 °C to +125 °C column; VCC = 3.0 V | 6 | ||
| LOW-level input voltage | VIL | 1.65 | V | -40 °C to +125 °C column; VCC = 5.5 V | 6 | ||
| HIGH-level output voltage | VOH | 1.9 | 2 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V | 6 | |
| HIGH-level output voltage | VOH | 2.9 | 3 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V | 6 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V | 6 | |
| HIGH-level output voltage | VOH | 2.4 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V | 6 | ||
| HIGH-level output voltage | VOH | 3.7 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V | 6 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V | 6 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = 50 μA; VCC = 3.0 V | 7 | |
| LOW-level output voltage | VOL | 0.55 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V | 7 | ||
| input leakage current | II | 2 | μA | -40 °C to +125 °C column; VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 7 | ||
| OFF-state output current | IOZ | -10 | 10 | μA | -40 °C to +125 °C column; VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V | 7 | |
| supply current | ICC | 80 | μA | -40 °C to +125 °C column; VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 7 | ||
| input capacitance | CI | 3 | 10 | pF | 7 | ||
| maximum frequency | fmax | 40 | 125 | MHz | -40 °C to +125 °C column; SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 3.0 V to 3.6 V | 9 | |
| maximum frequency | fmax | 90 | 170 | MHz | -40 °C to +125 °C column; SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 4.5 V to 5.5 V | 9 | |
| SHCP pulse width | tW | 5 | ns | -40 °C to +125 °C column; SHCP HIGH or LOW; see Fig. 6; VCC = 3.0 V to 3.6 V | 9 | ||
| STCP pulse width | tW | 5 | ns | -40 °C to +125 °C column; STCP HIGH or LOW; see Fig. 7; VCC = 3.0 V to 3.6 V | 9 | ||
| MR pulse width | tW | 5 | ns | -40 °C to +125 °C column; MR LOW; see Fig. 9; VCC = 3.0 V to 3.6 V | 9 | ||
| set-up time DS to SHCP | tsu | 3.5 | ns | -40 °C to +125 °C column; DS to SHCP; see Fig. 8; VCC = 3.0 V to 3.6 V | 9 | ||
| set-up time DS to SHCP | tsu | 3 | ns | -40 °C to +125 °C column; DS to SHCP; see Fig. 8; VCC = 4.5 V to 5.5 V | 9 | ||
| set-up time SHCP to STCP | tsu | 8.5 | ns | -40 °C to +125 °C column; SHCP to STCP; see Fig. 7; VCC = 3.0 V to 3.6 V | 9 | ||
| set-up time SHCP to STCP | tsu | 5 | ns | -40 °C to +125 °C column; SHCP to STCP; see Fig. 7; VCC = 4.5 V to 5.5 V | 9 | ||
| hold time DS to SHCP | th | 1.5 | ns | -40 °C to +125 °C column; DS to SHCP; see Fig. 8; VCC = 3.0 V to 3.6 V | 9 | ||
| hold time DS to SHCP | th | 2 | ns | -40 °C to +125 °C column; DS to SHCP; see Fig. 8; VCC = 4.5 V to 5.5 V | 9 | ||
| recovery time MR to SHCP | trec | 3 | ns | -40 °C to +125 °C column; MR to SHCP; see Fig. 9; VCC = 3.0 V to 3.6 V | 9 | ||
| recovery time MR to SHCP | trec | 2.5 | ns | -40 °C to +125 °C column; MR to SHCP; see Fig. 9; VCC = 4.5 V to 5.5 V | 9 | ||
| propagation delay SHCP to Q7S | tpd | 1 | 4 | 10.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 6 | 8 |
| propagation delay SHCP to Q7S | tpd | 1 | 5.4 | 12.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 6 | 8 |
| propagation delay STCP to Qn | tpd | 1 | 4.2 | 9.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 7 | 8 |
| propagation delay STCP to Qn | tpd | 1 | 5.5 | 11.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 7 | 8 |
| propagation delay MR to Q7S | tpd | 1 | 4.4 | 10 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 9 | 8 |
| propagation delay MR to Q7S | tpd | 1 | 5.6 | 12 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 9 | 8 |
| enable time OE to Qn | ten | 1 | 4 | 11 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 10 | 8 |
| enable time OE to Qn | ten | 1 | 5.3 | 13 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 10 | 8 |
| disable time OE to Qn | tdis | 1 | 3.8 | 10.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 10 | 8 |
CAD (KiCad official)
- Symbol:
74VHC595D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
74vhc595d-etched.step/74vhc595d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74vhc595d.step/74vhc595d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (20 pp, sha256
3190d1be143cb037, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74VHC595D
**Nexperia** · Shift Registers · SO-16
74VHC595D from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | tri_state | Parallel 3-state data output of storage register stage 1; it goes to high-impedance OFF-state when OE is HIGH. |
| 2 | Q2 | tri_state | Parallel 3-state data output of storage register stage 2; it goes to high-impedance OFF-state when OE is HIGH. |
| 3 | Q3 | tri_state | Parallel 3-state data output of storage register stage 3; it goes to high-impedance OFF-state when OE is HIGH. |
| 4 | Q4 | tri_state | Parallel 3-state data output of storage register stage 4; it goes to high-impedance OFF-state when OE is HIGH. |
| 5 | Q5 | tri_state | Parallel 3-state data output of storage register stage 5; it goes to high-impedance OFF-state when OE is HIGH. |
| 6 | Q6 | tri_state | Parallel 3-state data output of storage register stage 6; it goes to high-impedance OFF-state when OE is HIGH. |
| 7 | Q7 | tri_state | Parallel 3-state data output of storage register stage 7; it goes to high-impedance OFF-state when OE is HIGH. |
| 8 | GND | power_in | Ground reference (0 V) for all voltages in the datasheet. |
| 9 | Q7S | output | Serial standard data output of the 8-stage shift register used for cascading to another device; it is not disabled by OE. |
| 10 | MR | input | Asynchronous master reset, active LOW, that clears all 8 shift register stages and affects only the shift register, not the storage register. |
| 11 | SHCP | input | Shift register clock input; data is shifted through the register on each positive-going (LOW-to-HIGH) transition. |
| 12 | STCP | input | Storage register clock input; shift register contents are transferred to the storage register and parallel outputs on its positive-going transition. |
| 13 | OE | input | Output enable input, active LOW; when HIGH, outputs Q0 to Q7 are forced to the high-impedance OFF-state. |
| 14 | DS | input | Serial data input to shift register stage 0, clocked in on the positive-going SHCP transition. |
| 15 | Q0 | tri_state | Parallel 3-state data output of storage register stage 0; it goes to high-impedance OFF-state when OE is HIGH. |
| 16 | VCC | power_in | Supply voltage; the datasheet specifies 2.0 V to 5.5 V for 74VHC595 and 4.5 V to 5.5 V for 74VHCT595 in recommended operating conditions. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | | 7 | V | | 5 |
| input voltage | VI | -0.5 | | 7 | V | | 5 |
| input clamping current | IIK | -20 | | | mA | VI < -0.5 V | 6 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 6 |
| output current | IO | -25 | | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 6 |
| supply current | ICC | | | 75 | mA | | 6 |
| ground current | IGND | -75 | | | mA | | 6 |
| storage temperature | Tstg | -65 | | 150 | °C | | 6 |
| total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C | 6 |
| supply voltage (74VHC595) | VCC | 2 | 5 | 5.5 | V | | 6 |
| input voltage | VI | 0 | | 5.5 | V | | 6 |
| output voltage | VO | 0 | | | V | | 6 |
| ambient temperature | Tamb | -40 | 25 | 125 | °C | | 6 |
| input transition rise and fall rate | Δt/ΔV | | | 100 | ns/V | VCC = 3.0 V to 3.6 V | 6 |
| input transition rise and fall rate | Δt/ΔV | | | 20 | ns/V | VCC = 4.5 V to 5.5 V | 6 |
| HIGH-level input voltage | VIH | 1.5 | | | V | -40 °C to +125 °C column; VCC = 2.0 V | 6 |
| HIGH-level input voltage | VIH | 2.1 | | | V | -40 °C to +125 °C column; VCC = 3.0 V | 6 |
| HIGH-level input voltage | VIH | 3.85 | | | V | -40 °C to +125 °C column; VCC = 5.5 V | 6 |
| LOW-level input voltage | VIL | | | 0.5 | V | -40 °C to +125 °C column; VCC = 2.0 V | 6 |
| LOW-level input voltage | VIL | | | 0.9 | V | -40 °C to +125 °C column; VCC = 3.0 V | 6 |
| LOW-level input voltage | VIL | | | 1.65 | V | -40 °C to +125 °C column; VCC = 5.5 V | 6 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V | 6 |
| HIGH-level output voltage | VOH | 2.9 | 3 | | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V | 6 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V | 6 |
| HIGH-level output voltage | VOH | 2.4 | | | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V | 6 |
| HIGH-level output voltage | VOH | 3.7 | | | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V | 6 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V | 6 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = 50 μA; VCC = 3.0 V | 7 |
| LOW-level output voltage | VOL | | | 0.55 | V | -40 °C to +125 °C column; VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V | 7 |
| input leakage current | II | | | 2 | μA | -40 °C to +125 °C column; VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 7 |
| OFF-state output current | IOZ | -10 | | 10 | μA | -40 °C to +125 °C column; VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V | 7 |
| supply current | ICC | | | 80 | μA | -40 °C to +125 °C column; VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 7 |
| input capacitance | CI | | 3 | 10 | pF | | 7 |
| maximum frequency | fmax | 40 | 125 | | MHz | -40 °C to +125 °C column; SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 3.0 V to 3.6 V | 9 |
| maximum frequency | fmax | 90 | 170 | | MHz | -40 °C to +125 °C column; SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 4.5 V to 5.5 V | 9 |
| SHCP pulse width | tW | 5 | | | ns | -40 °C to +125 °C column; SHCP HIGH or LOW; see Fig. 6; VCC = 3.0 V to 3.6 V | 9 |
| STCP pulse width | tW | 5 | | | ns | -40 °C to +125 °C column; STCP HIGH or LOW; see Fig. 7; VCC = 3.0 V to 3.6 V | 9 |
| MR pulse width | tW | 5 | | | ns | -40 °C to +125 °C column; MR LOW; see Fig. 9; VCC = 3.0 V to 3.6 V | 9 |
| set-up time DS to SHCP | tsu | 3.5 | | | ns | -40 °C to +125 °C column; DS to SHCP; see Fig. 8; VCC = 3.0 V to 3.6 V | 9 |
| set-up time DS to SHCP | tsu | 3 | | | ns | -40 °C to +125 °C column; DS to SHCP; see Fig. 8; VCC = 4.5 V to 5.5 V | 9 |
| set-up time SHCP to STCP | tsu | 8.5 | | | ns | -40 °C to +125 °C column; SHCP to STCP; see Fig. 7; VCC = 3.0 V to 3.6 V | 9 |
| set-up time SHCP to STCP | tsu | 5 | | | ns | -40 °C to +125 °C column; SHCP to STCP; see Fig. 7; VCC = 4.5 V to 5.5 V | 9 |
| hold time DS to SHCP | th | 1.5 | | | ns | -40 °C to +125 °C column; DS to SHCP; see Fig. 8; VCC = 3.0 V to 3.6 V | 9 |
| hold time DS to SHCP | th | 2 | | | ns | -40 °C to +125 °C column; DS to SHCP; see Fig. 8; VCC = 4.5 V to 5.5 V | 9 |
| recovery time MR to SHCP | trec | 3 | | | ns | -40 °C to +125 °C column; MR to SHCP; see Fig. 9; VCC = 3.0 V to 3.6 V | 9 |
| recovery time MR to SHCP | trec | 2.5 | | | ns | -40 °C to +125 °C column; MR to SHCP; see Fig. 9; VCC = 4.5 V to 5.5 V | 9 |
| propagation delay SHCP to Q7S | tpd | 1 | 4 | 10.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 6 | 8 |
| propagation delay SHCP to Q7S | tpd | 1 | 5.4 | 12.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 6 | 8 |
| propagation delay STCP to Qn | tpd | 1 | 4.2 | 9.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 7 | 8 |
| propagation delay STCP to Qn | tpd | 1 | 5.5 | 11.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 7 | 8 |
| propagation delay MR to Q7S | tpd | 1 | 4.4 | 10 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 9 | 8 |
| propagation delay MR to Q7S | tpd | 1 | 5.6 | 12 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 9 | 8 |
| enable time OE to Qn | ten | 1 | 4 | 11 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 10 | 8 |
| enable time OE to Qn | ten | 1 | 5.3 | 13 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 10 | 8 |
| disable time OE to Qn | tdis | 1 | 3.8 | 10.5 | ns | -40 °C to +125 °C column; VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 10 | 8 |
## CAD (KiCad official)
- Symbol: `74VHC595D`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files: `74vhc595d-etched.step` / `74vhc595d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74vhc595d.step` / `74vhc595d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914163989024768) (20 pp, sha256 `3190d1be143cb037`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74vhc595d-datasheet.pdf)