component
74VHC161FT
Public Made by Adomby adom
TOSHIBA Counters, Dividers, TSSOP16B. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74VHC161FT
TOSHIBA · Counters, Dividers · TSSOP16B
74VHC161FT from TOSHIBA, in a TSSOP16B. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active-low clear input that clears the counter asynchronously on the 74VHC161FT; accepts 0 to 5.5 V regardless of supply. |
| 2 | CK | input | Clock input, active on the rising edge, with presetting synchronous to the rising edge of CK. |
| 3 | A | input | Preset data input A (logic level loaded into QA when LOAD is low), 0 to 5.5 V input range. |
| 4 | B | input | Preset data input B (logic level loaded into QB when LOAD is low), 0 to 5.5 V input range. |
| 5 | C | input | Preset data input C (logic level loaded into QC when LOAD is low), 0 to 5.5 V input range. |
| 6 | D | input | Preset data input D (logic level loaded into QD when LOAD is low), 0 to 5.5 V input range. |
| 7 | ENP | input | Count enable input P, used with ENT to enable easy cascading of counters. |
| 8 | GND | power_in | Ground pin (0 V). |
| 9 | LOAD | input | Active-low synchronous load input that presets the counter from A-D on the rising edge of CK. |
| 10 | ENT | input | Count enable input T, which also gates the carry output (Carry = ENT·QA·QB·QC·QD) for cascading. |
| 11 | QD | output | Counter output QD, the most significant bit of the 4-bit binary counter. |
| 12 | QC | output | Counter output QC of the 4-bit binary counter. |
| 13 | QB | output | Counter output QB of the 4-bit binary counter. |
| 14 | QA | output | Counter output QA, the least significant bit of the 4-bit binary counter. |
| 15 | Carry Output | output | Carry output (Carry = ENT·QA·QB·QC·QD) provided for cascading counters without external gates. |
| 16 | VCC | power_in | Supply voltage pin, operating range 2.0 V to 5.5 V (absolute maximum -0.5 to 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | TSSOP16B |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 6 | ||
| Input voltage | VIN | -0.5 | 7 | V | 6 | ||
| Output voltage | VOUT | -0.5 | V | 6 | |||
| Input diode current | IIK | -20 | mA | 6 | |||
| Output diode current | IOK | -20 | 20 | mA | 6 | ||
| Output current | IOUT | -25 | 25 | mA | 6 | ||
| VCC/ground current | ICC | -50 | 50 | mA | 6 | ||
| Power dissipation | PD | 180 | mW | Ta = -40 to 85 °C | 6 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Supply voltage | VCC | 2 | 5.5 | V | 6 | ||
| Input voltage | VIN | 0 | 5.5 | V | 6 | ||
| Output voltage | VOUT | 0 | V | 6 | |||
| Operating temperature | Topr | -40 | 125 | °C | 6 | ||
| Input rise and fall times | dt/dv | 0 | 100 | ns/V | VCC = 3.3 ± 0.3 V | 6 | |
| Input rise and fall times | dt/dv | 0 | 20 | ns/V | VCC = 5 ± 0.5 V | 6 | |
| High-level input voltage | VIH | 1.5 | V | Ta = 25 °C; VCC = 2.0 V | 7 | ||
| Low-level input voltage | VIL | 0.5 | V | Ta = 25 °C; VCC = 2.0 V | 7 | ||
| High-level output voltage | VOH | 1.9 | V | Ta = 25 °C; VCC = 2.0 V; IOH = -50 µA | 7 | ||
| High-level output voltage | VOH | 2.9 | V | Ta = 25 °C; VCC = 3.0 V; IOH = -50 µA | 7 | ||
| High-level output voltage | VOH | 4.4 | V | Ta = 25 °C; VCC = 4.5 V; IOH = -50 µA | 7 | ||
| High-level output voltage | VOH | 2.58 | V | Ta = 25 °C; VCC = 3.0 V; IOH = -4 mA | 7 | ||
| High-level output voltage | VOH | 3.94 | V | Ta = 25 °C; VCC = 4.5 V; IOH = -8 mA | 7 | ||
| Low-level output voltage | VOL | 0.1 | V | Ta = 25 °C; VCC = 2.0 V; IOL = 50 µA | 7 | ||
| Low-level output voltage | VOL | 0.36 | V | Ta = 25 °C; VCC = 3.0 V; IOL = 4 mA | 7 | ||
| Input leakage current | IIN | -0.1 | 0.1 | µA | Ta = 25 °C; VIN = 5.5 V or GND; VCC = 0 to 5.5 V | 7 | |
| Quiescent supply current | ICC | 4 | µA | Ta = 25 °C; VIN = VCC or GND; VCC = 5.5 V | 7 | ||
| Minimum pulse width (CK) | tw(L),tw(H) | 5 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 1; tr = tf = 3 ns | 8 | ||
| Minimum pulse width (CLR) | tw(L) | 5 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 4; tr = tf = 3 ns | 8 | ||
| Minimum setup time (A,B,C,D) | tSt | 5.5 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 2; tr = tf = 3 ns | 8 | ||
| Minimum setup time (A,B,C,D) | tSt | 4.5 | ns | Ta = 25 °C; VCC = 5.0 ± 0.5 V; Figure 2; tr = tf = 3 ns | 8 | ||
| Minimum setup time (LOAD) | tSt | 8 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 2; tr = tf = 3 ns | 8 | ||
| Minimum setup time (LOAD) | tSt | 5 | ns | Ta = 25 °C; VCC = 5.0 ± 0.5 V; Figure 2; tr = tf = 3 ns | 8 | ||
| Minimum setup time (ENT,ENP) | tSt | 7.5 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 3; tr = tf = 3 ns | 8 | ||
| Minimum setup time (ENT,ENP) | tSt | 5 | ns | Ta = 25 °C; VCC = 5.0 ± 0.5 V; Figure 3; tr = tf = 3 ns | 8 | ||
| Minimum setup time (CLR) | tSt | 4 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 5; tr = tf = 3 ns | 8 | ||
| Minimum setup time (CLR) | tSt | 3.5 | ns | Ta = 25 °C; VCC = 5.0 ± 0.5 V; Figure 5; tr = tf = 3 ns | 8 | ||
| Minimum hold time | th | 1 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 2, Figure 3; tr = tf = 3 ns | 8 | ||
| Minimum hold time (CLR) | th | 1 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 5; tr = tf = 3 ns | 8 | ||
| Minimum hold time (CLR) | th | 1.5 | ns | Ta = 25 °C; VCC = 5.0 ± 0.5 V; Figure 5; tr = tf = 3 ns | 8 | ||
| Minimum removal time (CLR) | trem | 2.5 | ns | Ta = 25 °C; VCC = 3.3 ± 0.3 V; Figure 4; tr = tf = 3 ns | 8 | ||
| Minimum removal time (CLR) | trem | 1.5 | ns | Ta = 25 °C; VCC = 5.0 ± 0.5 V; Figure 4; tr = tf = 3 ns | 8 | ||
| Maximum clock frequency | fMAX | 80 | 130 | MHz | Ta = 25 °C; VCC = 3.3 ± 0.3 V; CL = 15 pF | 10 | |
| Maximum clock frequency | fMAX | 55 | 85 | MHz | Ta = 25 °C; VCC = 3.3 ± 0.3 V; CL = 50 pF | 10 | |
| Maximum clock frequency | fMAX | 135 | 185 | MHz | Ta = 25 °C; VCC = 5.0 ± 0.5 V; CL = 15 pF | 10 | |
| Input capacitance | CIN | 4 | 10 | pF | Ta = 25 °C | 10 |
CAD (KiCad official)
- Symbol:
74VHC161FT - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP16B (KiCad packages3D, STEP)
- 3D model files:
74vhc161ft-etched.step/74vhc161ft-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74vhc161ft.step/74vhc161ft.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (17 pp, sha256
40d97dedc9e79c02, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).