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74VHC112MTCX

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onsemi Flip Flops, TSSOP-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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74VHC112MTCX

onsemi · Flip Flops · TSSOP-16

74VHC112MTCX from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK1 input Clock pulse input of flip-flop 1, active on the falling (HIGH-to-LOW) edge; input range 0V to 5.5V and it must not float.
2 K1 input K data input of flip-flop 1, which must be at its desired state during the setup and hold times around the falling clock edge; input range 0V to 5.5V and it must not float.
3 J1 input J data input of flip-flop 1, which must be at its desired state during the setup and hold times around the falling clock edge; input range 0V to 5.5V and it must not float.
4 PR1 input Direct preset input of flip-flop 1, active LOW, which prevents clocking and forces Q1 HIGH; input range 0V to 5.5V and it must not float.
5 Q1 output True output of flip-flop 1, rated for up to ±25mA DC output current.
6 Q1_N output Complementary (inverted) output of flip-flop 1, rated for up to ±25mA DC output current.
7 Q2_N output Complementary (inverted) output of flip-flop 2, rated for up to ±25mA DC output current.
8 GND power_in Ground pin; the maximum DC VCC/GND current is ±50mA.
9 Q2 output True output of flip-flop 2, rated for up to ±25mA DC output current.
10 PR2 input Direct preset input of flip-flop 2, active LOW, which prevents clocking and forces Q2 HIGH; input range 0V to 5.5V and it must not float.
11 J2 input J data input of flip-flop 2, which must be at its desired state during the setup and hold times around the falling clock edge; input range 0V to 5.5V and it must not float.
12 K2 input K data input of flip-flop 2, which must be at its desired state during the setup and hold times around the falling clock edge; input range 0V to 5.5V and it must not float.
13 CLK2 input Clock pulse input of flip-flop 2, active on the falling (HIGH-to-LOW) edge; input range 0V to 5.5V and it must not float.
14 CLR2 input Direct clear input of flip-flop 2, active LOW, which prevents clocking and forces Q2 LOW (Q2 bar HIGH); input range 0V to 5.5V and it must not float.
15 CLR1 input Direct clear input of flip-flop 1, active LOW, which prevents clocking and forces Q1 LOW (Q1 bar HIGH); input range 0V to 5.5V and it must not float.
16 VCC power_in Positive supply voltage, recommended operating range 2.0V to 5.5V (absolute maximum 7.0V).

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -0.5 7 V 4
DC Input Voltage VIN -0.5 7 V 4
Input Diode Current IIK -20 mA 4
Output Diode Current IOK -20 20 mA 4
DC Output Current IOUT -25 25 mA 4
DC VCC/GND Current ICC -50 50 mA 4
Storage Temperature TSTG -65 150 °C 4
Lead Temperature TL 260 °C Soldering, 10 seconds 4
Supply Voltage VCC 2 5.5 V 4
Input Voltage VIN 0 5.5 V 4
Operating Temperature TOPR -40 85 °C 4
Input Rise and Fall Time tr, tf 0 100 ns/V VCC=3.3 V ±0.3 V 4
Input Rise and Fall Time tr, tf 0 20 ns/V VCC=5.0 V ±0.5 V 4
HIGH Level Input Voltage VIH 1.5 V VCC=2.0 V; TA=-40 to +85°C 5
LOW Level Input Voltage VIL 0.5 V VCC=2.0 V; TA=-40 to +85°C 5
HIGH Level Output Voltage VOH 1.9 2 V VCC=2.0 V; VIN=VIH or VIL; IOH=-50µA; TA=25°C 5
HIGH Level Output Voltage VOH 1.9 V VCC=2.0 V; VIN=VIH or VIL; IOH=-50µA; TA=-40 to +85°C 5
HIGH Level Output Voltage VOH 2.9 3 V VCC=3.0 V; VIN=VIH or VIL; IOH=-50µA; TA=25°C 5
HIGH Level Output Voltage VOH 2.9 V VCC=3.0 V; VIN=VIH or VIL; IOH=-50µA; TA=-40 to +85°C 5
HIGH Level Output Voltage VOH 4.4 4.5 V VCC=4.5 V; VIN=VIH or VIL; IOH=-50µA; TA=25°C 5
HIGH Level Output Voltage VOH 4.4 V VCC=4.5 V; VIN=VIH or VIL; IOH=-50µA; TA=-40 to +85°C 5
HIGH Level Output Voltage VOH 2.58 V VCC=3.0 V; VIN=VIH or VIL; IOH=-4mA; TA=25°C 5
HIGH Level Output Voltage VOH 2.48 V VCC=3.0 V; VIN=VIH or VIL; IOH=-4mA; TA=-40 to +85°C 5
HIGH Level Output Voltage VOH 3.94 V VCC=4.5 V; VIN=VIH or VIL; IOH=-8mA; TA=25°C 5
HIGH Level Output Voltage VOH 3.8 V VCC=4.5 V; VIN=VIH or VIL; IOH=-8mA; TA=-40 to +85°C 5
LOW Level Output Voltage VOL 0 0.1 V VCC=2.0 V; VIN=VIH or VIL; IOL=50µA; TA=25°C 5
LOW Level Output Voltage VOL 0.1 V VCC=2.0 V; VIN=VIH or VIL; IOL=50µA; TA=-40 to +85°C 5
LOW Level Output Voltage VOL 0.36 V VCC=3.0 V; VIN=VIH or VIL; IOL=4mA; TA=25°C 5
LOW Level Output Voltage VOL 0.44 V VCC=3.0 V; VIN=VIH or VIL; IOL=4mA; TA=-40 to +85°C 5
Input Leakage Current IIN -0.1 0.1 µA VCC=0-5.5 V; VIN=5.5 V or GND; TA=25°C 5
Input Leakage Current IIN -1 1 µA VCC=0-5.5 V; VIN=5.5 V or GND; TA=-40 to +85°C 5
Quiescent Supply Current ICC 2 µA VCC=5.5 V; VIN=VCC or GND; TA=25°C 5
Quiescent Supply Current ICC 20 µA VCC=5.5 V; VIN=VCC or GND; TA=-40 to +85°C 5
Maximum Clock Frequency fMAX 100 150 MHz VCC=3.3 V ±0.3 V; CL=15 pF; TA=-40 to +85°C 6
Maximum Clock Frequency fMAX 80 120 MHz VCC=3.3 V ±0.3 V; CL=50 pF; TA=-40 to +85°C 6
Maximum Clock Frequency fMAX 135 200 MHz VCC=5.0 V ±0.5 V; CL=15 pF; TA=-40 to +85°C 6
Maximum Clock Frequency fMAX 110 185 MHz VCC=5.0 V ±0.5 V; CL=50 pF; TA=-40 to +85°C 6
Propagation Delay Time (CP to Qn or Qn-bar) tPLH, tPHL 1 8.5 13.4 ns VCC=3.3 V ±0.3 V; CL=15 pF; TA=-40 to +85°C 6
Propagation Delay Time (CP to Qn or Qn-bar) tPLH, tPHL 1 10 16.5 ns VCC=3.3 V ±0.3 V; CL=50 pF; TA=-40 to +85°C 6
Propagation Delay Time (CP to Qn or Qn-bar) tPLH, tPHL 1 5.1 8.8 ns VCC=5.0 V ±0.5 V; CL=15 pF; TA=-40 to +85°C 6
Propagation Delay Time (CP to Qn or Qn-bar) tPLH, tPHL 1 6.3 12 ns VCC=5.0 V ±0.5 V; CL=50 pF; TA=-40 to +85°C 6
Propagation Delay Time (PR or CLR to Qn or Qn-bar) tPLH, tPHL 1 6.7 11.7 ns VCC=3.3 V ±0.3 V; CL=15 pF; TA=-40 to +85°C 6
Propagation Delay Time (PR or CLR to Qn or Qn-bar) tPLH, tPHL 1 9.7 15 ns VCC=3.3 V ±0.3 V; CL=50 pF; TA=-40 to +85°C 6
Propagation Delay Time (PR or CLR to Qn or Qn-bar) tPLH, tPHL 1 4.6 8 ns VCC=5.0 V ±0.5 V; CL=15 pF; TA=-40 to +85°C 6
Propagation Delay Time (PR or CLR to Qn or Qn-bar) tPLH, tPHL 1 6.4 11 ns VCC=5.0 V ±0.5 V; CL=50 pF; TA=-40 to +85°C 6
Input Capacitance CIN 4 10 pF VCC=Open; TA=-40 to +85°C 6
Minimum Pulse Width (CP or CLR or PR) tW 5 5 ns VCC=3.3 V ±0.3 V 6
Minimum Setup Time (Jn or Kn to CPn) tS 5 5 ns VCC=3.3 V ±0.3 V 6
Minimum Setup Time (Jn or Kn to CPn) tS 4 4 ns VCC=5.0 V ±0.5 V 6
Minimum Hold Time (Jn or Kn to CPn) tH 1 1 ns VCC=3.3 V ±0.3 V 6
Minimum Recovery Time (CLR or PR to CP) tREC 6 6 ns VCC=3.3 V ±0.3 V 6
Minimum Recovery Time (CLR or PR to CP) tREC 5 5 ns VCC=5.0 V ±0.5 V 6

CAD (KiCad official)

  • Symbol: 74VHC112MTCX
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74vhc112mtcx-etched.step / 74vhc112mtcx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74vhc112mtcx.step / 74vhc112mtcx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (11 pp, sha256 db7cd7eec5a9d15b, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF