component
74VHC00MTCX
Public Made by Adomby adom
onsemi Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74VHC00MTCX
onsemi · Logic Gates · TSSOP-14
74VHC00MTCX from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Gate 0 input A; unused inputs must be held HIGH or LOW and may not float, and inputs accept 0 V to 5.5 V regardless of VCC. |
| 2 | B0 | input | Gate 0 input B; unused inputs must be held HIGH or LOW and may not float, and inputs accept 0 V to 5.5 V regardless of VCC. |
| 3 | O0 | output | Gate 0 NAND output, with buffered CMOS output stage; output swing is limited to 0 V to VCC. |
| 4 | A1 | input | Gate 1 input A; unused inputs must be held HIGH or LOW and may not float, and inputs accept 0 V to 5.5 V regardless of VCC. |
| 5 | B1 | input | Gate 1 input B; unused inputs must be held HIGH or LOW and may not float, and inputs accept 0 V to 5.5 V regardless of VCC. |
| 6 | O1 | output | Gate 1 NAND output, with buffered CMOS output stage; output swing is limited to 0 V to VCC. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | O2 | output | Gate 2 NAND output, with buffered CMOS output stage; output swing is limited to 0 V to VCC. |
| 9 | A2 | input | Gate 2 input A; unused inputs must be held HIGH or LOW and may not float, and inputs accept 0 V to 5.5 V regardless of VCC. |
| 10 | B2 | input | Gate 2 input B; unused inputs must be held HIGH or LOW and may not float, and inputs accept 0 V to 5.5 V regardless of VCC. |
| 11 | O3 | output | Gate 3 NAND output, with buffered CMOS output stage; output swing is limited to 0 V to VCC. |
| 12 | A3 | input | Gate 3 input A; unused inputs must be held HIGH or LOW and may not float, and inputs accept 0 V to 5.5 V regardless of VCC. |
| 13 | B3 | input | Gate 3 input B; unused inputs must be held HIGH or LOW and may not float, and inputs accept 0 V to 5.5 V regardless of VCC. |
| 14 | VCC | power_in | Positive supply; recommended DC supply range is 2.0 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (Recommended) | VCC | 2 | 5.5 | V | 2 | ||
| DC Input Voltage (Recommended, Note 3) | VIN | 0 | 5.5 | V | 2 | ||
| Operating Temperature | TA | -40 | 85 | C | 2 | ||
| Input Rise or Fall Rate | tr, tf | 0 | 100 | ns/V | VCC = 3.0 V to 3.6 V | 2 | |
| Input Rise or Fall Rate | tr, tf | 0 | 20 | ns/V | VCC = 4.5 V to 5.5 V | 2 | |
| DC Supply Voltage (Absolute Maximum) | VCC | -0.5 | 6.5 | V | 2 | ||
| DC Input Voltage (Absolute Maximum) | VIN | -0.5 | 6.5 | V | 2 | ||
| DC Input Current, per Pin | IIN | 20 | mA | 2 | |||
| DC Output Current, per Pin | IOUT | 25 | mA | 2 | |||
| DC Supply Current, VCC and GND Pins | ICC | 50 | mA | 2 | |||
| Input Clamp Current | IIK | -20 | mA | 2 | |||
| Output Clamp Current | IOK | 20 | mA | 2 | |||
| Storage Temperature Range | TSTG | -65 | 150 | C | 2 | ||
| Lead Temperature | TL | 260 | C | 1 mm from case for 10 seconds | 2 | ||
| Junction Temperature Under Bias | TJ | 150 | C | 2 | |||
| Power Dissipation in Still Air | PD | 833 | mW | Still air at 25C | 2 | ||
| ESD Withstand Voltage | VESD | 2000 | V | Human Body Model | 2 | ||
| Thermal Resistance, Junction to Ambient (Note 1) | θJA | 150 | C/W | Minimum pad spacing on FR4, 2-oz copper, no airflow, per JESD51-7 | 2 | ||
| HIGH Level Input Voltage | VIH | 1.5 | V | VCC = 2.0 V; TA = 25C | 3 | ||
| LOW Level Input Voltage | VIL | 0.5 | V | VCC = 2.0 V; TA = 25C | 3 | ||
| HIGH Level Output Voltage | VOH | 1.9 | 2 | V | VIN = VIH or VIL; IOH = -50 µA; VCC = 2.0 V; TA = 25C | 3 | |
| HIGH Level Output Voltage | VOH | 1.9 | V | VIN = VIH or VIL; IOH = -50 µA; VCC = 2.0 V; TA = -40C to +85C | 3 | ||
| HIGH Level Output Voltage | VOH | 2.9 | 3 | V | VIN = VIH or VIL; IOH = -50 µA; VCC = 3.0 V; TA = 25C | 3 | |
| HIGH Level Output Voltage | VOH | 2.9 | V | VIN = VIH or VIL; IOH = -50 µA; VCC = 3.0 V; TA = -40C to +85C | 3 | ||
| HIGH Level Output Voltage | VOH | 4.4 | 4.5 | V | VIN = VIH or VIL; IOH = -50 µA; VCC = 4.5 V; TA = 25C | 3 | |
| HIGH Level Output Voltage | VOH | 4.4 | V | VIN = VIH or VIL; IOH = -50 µA; VCC = 4.5 V; TA = -40C to +85C | 3 | ||
| HIGH Level Output Voltage | VOH | 2.58 | V | VCC = 3.0 V; IOH = -4 mA; TA = 25C | 3 | ||
| HIGH Level Output Voltage | VOH | 2.48 | V | VCC = 3.0 V; IOH = -4 mA; TA = -40C to +85C | 3 | ||
| HIGH Level Output Voltage | VOH | 3.94 | V | VCC = 4.5 V; IOH = -8 mA; TA = 25C | 3 | ||
| HIGH Level Output Voltage | VOH | 3.8 | V | VCC = 4.5 V; IOH = -8 mA; TA = -40C to +85C | 3 | ||
| LOW Level Output Voltage | VOL | 0 | 0.1 | V | VIN = VIH or VIL; IOL = 50 µA; VCC = 2.0 V; TA = 25C | 3 | |
| LOW Level Output Voltage | VOL | 0.1 | V | VIN = VIH or VIL; IOL = 50 µA; VCC = 2.0 V; TA = -40C to +85C | 3 | ||
| LOW Level Output Voltage | VOL | 0.36 | V | VCC = 3.0 V; IOL = 4 mA; TA = 25C | 3 | ||
| LOW Level Output Voltage | VOL | 0.44 | V | VCC = 3.0 V; IOL = 4 mA; TA = -40C to +85C | 3 | ||
| Input Leakage Current | IIN | 0.1 | µA | VCC = 0-5.5 V; VIN = 5.5 V or GND; TA = 25C | 3 | ||
| Input Leakage Current | IIN | 1 | µA | VCC = 0-5.5 V; VIN = 5.5 V or GND; TA = -40C to +85C | 3 | ||
| Quiescent Supply Current | ICC | 2 | µA | VCC = 5.5 V; VIN = VCC or GND; TA = 25C | 3 | ||
| Quiescent Supply Current | ICC | 20 | µA | VCC = 5.5 V; VIN = VCC or GND; TA = -40C to +85C | 3 | ||
| Quiet Output Maximum Dynamic VOL | VOLP | 0.3 | 0.8 | V | VCC = 5.0 V; CL = 50 pF; TA = 25C | 3 | |
| Quiet Output Minimum Dynamic VOL | VOLV | -0.8 | -0.3 | V | VCC = 5.0 V; CL = 50 pF; TA = 25C | 3 | |
| Minimum HIGH Level Dynamic Input Voltage | VIHD | 3.5 | V | VCC = 5.0 V; CL = 50 pF; TA = 25C | 3 | ||
| Maximum LOW Level Dynamic Input Voltage | VILD | 1.5 | V | VCC = 5.0 V; CL = 50 pF; TA = 25C | 3 | ||
| Propagation Delay | tPLH, tPHL | 5.5 | 7.9 | ns | VCC = 3.3 V ±0.3 V; CL ≤ 15 pF; TA = 25C | 3 | |
| Propagation Delay | tPLH, tPHL | 1 | 9.5 | ns | VCC = 3.3 V ±0.3 V; CL ≤ 15 pF; TA = -40C to +85C | 3 | |
| Propagation Delay | tPLH, tPHL | 8 | 11.4 | ns | VCC = 3.3 V ±0.3 V; CL ≤ 50 pF; TA = 25C | 3 | |
| Propagation Delay | tPLH, tPHL | 1 | 13 | ns | VCC = 3.3 V ±0.3 V; CL ≤ 50 pF; TA = -40C to +85C | 3 | |
| Propagation Delay | tPLH, tPHL | 3.7 | 5.5 | ns | VCC = 5.0 V ±0.5 V; CL ≤ 15 pF; TA = 25C | 3 | |
| Propagation Delay | tPLH, tPHL | 1 | 6.5 | ns | VCC = 5.0 V ±0.5 V; CL ≤ 15 pF; TA = -40C to +85C | 3 | |
| Propagation Delay | tPLH, tPHL | 5.2 | 7.5 | ns | VCC = 5.0 V ±0.5 V; CL ≤ 50 pF; TA = 25C | 3 | |
| Propagation Delay | tPLH, tPHL | 1 | 8.5 | ns | VCC = 5.0 V ±0.5 V; CL ≤ 50 pF; TA = -40C to +85C | 3 | |
| Input Capacitance | CIN | 4 | 10 | pF | VCC open; TA = 25C | 3 | |
| Input Capacitance | CIN | 10 | pF | VCC open; TA = -40C to +85C | 3 |
CAD (KiCad official)
- Symbol:
74VHC00MTCX - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74vhc00mtcx-etched.step/74vhc00mtcx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74vhc00mtcx.step/74vhc00mtcx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (6 pp, sha256
6a0e264fed386fd4, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).