component
74VHC00FT
Public Made by Adomby adom
TOSHIBA Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74VHC00FT
TOSHIBA · Logic Gates · TSSOP-14
74VHC00FT from TOSHIBA, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A; inputs accept 0 to 5.5 V regardless of supply voltage, and unused inputs must be tied to VCC or GND. |
| 2 | 1B | input | Gate 1 input B; inputs accept 0 to 5.5 V regardless of supply voltage, and unused inputs must be tied to VCC or GND. |
| 3 | 1Y | output | Gate 1 NAND output, swings 0 to VCC. |
| 4 | 2A | input | Gate 2 input A; inputs accept 0 to 5.5 V regardless of supply voltage, and unused inputs must be tied to VCC or GND. |
| 5 | 2B | input | Gate 2 input B; inputs accept 0 to 5.5 V regardless of supply voltage, and unused inputs must be tied to VCC or GND. |
| 6 | 2Y | output | Gate 2 NAND output, swings 0 to VCC. |
| 7 | GND | power_in | Ground, 0 V reference. |
| 8 | 3Y | output | Gate 3 NAND output, swings 0 to VCC. |
| 9 | 3A | input | Gate 3 input A; inputs accept 0 to 5.5 V regardless of supply voltage, and unused inputs must be tied to VCC or GND. |
| 10 | 3B | input | Gate 3 input B; inputs accept 0 to 5.5 V regardless of supply voltage, and unused inputs must be tied to VCC or GND. |
| 11 | 4Y | output | Gate 4 NAND output, swings 0 to VCC. |
| 12 | 4A | input | Gate 4 input A; inputs accept 0 to 5.5 V regardless of supply voltage, and unused inputs must be tied to VCC or GND. |
| 13 | 4B | input | Gate 4 input B; inputs accept 0 to 5.5 V regardless of supply voltage, and unused inputs must be tied to VCC or GND. |
| 14 | VCC | power_in | Positive supply, operating range 2.0 V to 5.5 V (absolute maximum -0.5 to 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; Ta = 25 °C | 4 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; Ta = 25 °C | 4 | ||
| High-level output voltage | VOH | 1.9 | 2 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 2.0 V; Ta = 25 °C | 4 | |
| High-level output voltage | VOH | 2.9 | 3 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 3.0 V; Ta = 25 °C | 4 | |
| High-level output voltage | VOH | 4.4 | 4.5 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 4.5 V; Ta = 25 °C | 4 | |
| High-level output voltage | VOH | 2.58 | V | IOH = -4 mA; VIN = VIH or VIL; VCC = 3.0 V; Ta = 25 °C | 4 | ||
| High-level output voltage | VOH | 3.94 | V | IOH = -8 mA; VIN = VIH or VIL; VCC = 4.5 V; Ta = 25 °C | 4 | ||
| Low-level output voltage | VOL | 0 | 0.1 | V | IOL = 50 µA; VIN = VIH or VIL; VCC = 2.0 V; Ta = 25 °C | 4 | |
| Low-level output voltage | VOL | 0.36 | V | IOL = 4 mA; VIN = VIH or VIL; VCC = 3.0 V; Ta = 25 °C | 4 | ||
| Input leakage current | IIN | -0.1 | 0.1 | µA | VIN = 5.5 V or GND; VCC = 0 to 5.5 V; Ta = 25 °C | 4 | |
| Quiescent supply current | ICC | 2 | µA | VIN = VCC or GND; VCC = 5.5 V; Ta = 25 °C | 4 | ||
| High-level output voltage | VOH | 1.9 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 2.0 V; Ta = -40 to 85 °C | 4 | ||
| High-level output voltage | VOH | 2.9 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 3.0 V; Ta = -40 to 85 °C | 4 | ||
| High-level output voltage | VOH | 4.4 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 4.5 V; Ta = -40 to 85 °C | 4 | ||
| High-level output voltage | VOH | 2.48 | V | IOH = -4 mA; VIN = VIH or VIL; VCC = 3.0 V; Ta = -40 to 85 °C | 4 | ||
| High-level output voltage | VOH | 3.8 | V | IOH = -8 mA; VIN = VIH or VIL; VCC = 4.5 V; Ta = -40 to 85 °C | 4 | ||
| Low-level output voltage | VOL | 0.1 | V | IOL = 50 µA; VIN = VIH or VIL; VCC = 2.0 V; Ta = -40 to 85 °C | 4 | ||
| Low-level output voltage | VOL | 0.44 | V | IOL = 4 mA; VIN = VIH or VIL; VCC = 3.0 V; Ta = -40 to 85 °C | 4 | ||
| Input leakage current | IIN | -1 | 1 | µA | VIN = 5.5 V or GND; VCC = 0 to 5.5 V; Ta = -40 to 85 °C | 4 | |
| Quiescent supply current | ICC | 20 | µA | VIN = VCC or GND; VCC = 5.5 V; Ta = -40 to 85 °C | 4 | ||
| High-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; Ta = -40 to 125 °C | 5 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; Ta = -40 to 125 °C | 5 | ||
| High-level output voltage | VOH | 1.9 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 2.0 V; Ta = -40 to 125 °C | 5 | ||
| High-level output voltage | VOH | 2.9 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 3.0 V; Ta = -40 to 125 °C | 5 | ||
| High-level output voltage | VOH | 4.4 | V | IOH = -50 µA; VIN = VIH or VIL; VCC = 4.5 V; Ta = -40 to 125 °C | 5 | ||
| High-level output voltage | VOH | 2.4 | V | IOH = -4 mA; VIN = VIH or VIL; VCC = 3.0 V; Ta = -40 to 125 °C | 5 | ||
| High-level output voltage | VOH | 3.7 | V | IOH = -8 mA; VIN = VIH or VIL; VCC = 4.5 V; Ta = -40 to 125 °C | 5 | ||
| Low-level output voltage | VOL | 0.1 | V | IOL = 50 µA; VIN = VIH or VIL; VCC = 2.0 V; Ta = -40 to 125 °C | 5 | ||
| Low-level output voltage | VOL | 0.55 | V | IOL = 4 mA; VIN = VIH or VIL; VCC = 3.0 V; Ta = -40 to 125 °C | 5 | ||
| Input leakage current | IIN | -2 | 2 | µA | VIN = 5.5 V or GND; VCC = 0 to 5.5 V; Ta = -40 to 125 °C | 5 | |
| Quiescent supply current | ICC | 40 | µA | VIN = VCC or GND; VCC = 5.5 V; Ta = -40 to 125 °C | 5 | ||
| Propagation delay time | tPLH,tPHL | 5.5 | 7.9 | ns | VCC = 3.3 ± 0.3 V; CL = 15 pF; tr = tf = 3 ns; Ta = 25 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 8 | 11.4 | ns | VCC = 3.3 ± 0.3 V; CL = 50 pF; tr = tf = 3 ns; Ta = 25 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 3.7 | 5.5 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; tr = tf = 3 ns; Ta = 25 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 5.24 | 7.5 | ns | VCC = 5.0 ± 0.5 V; CL = 50 pF; tr = tf = 3 ns; Ta = 25 °C | 5 | |
| Input capacitance | CIN | 10 | pF | Ta = 25 °C | 5 | ||
| Propagation delay time | tPLH,tPHL | 1 | 9.5 | ns | VCC = 3.3 ± 0.3 V; CL = 15 pF; tr = tf = 3 ns; Ta = -40 to 85 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 1 | 13 | ns | VCC = 3.3 ± 0.3 V; CL = 50 pF; tr = tf = 3 ns; Ta = -40 to 85 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 1 | 6.5 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; tr = tf = 3 ns; Ta = -40 to 85 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 1 | 8.5 | ns | VCC = 5.0 ± 0.5 V; CL = 50 pF; tr = tf = 3 ns; Ta = -40 to 85 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 1 | 11 | ns | VCC = 3.3 ± 0.3 V; CL = 15 pF; tr = tf = 3 ns; Ta = -40 to 125 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 1 | 14.5 | ns | VCC = 3.3 ± 0.3 V; CL = 50 pF; tr = tf = 3 ns; Ta = -40 to 125 °C | 5 | |
| Propagation delay time | tPLH,tPHL | 1 | 7.5 | ns | VCC = 5.0 ± 0.5 V; CL = 15 pF; tr = tf = 3 ns; Ta = -40 to 125 °C | 5 | |
| Supply voltage (recommended operating) | VCC | 2 | 5.5 | V | 3 | ||
| Operating temperature | Topr | -40 | 125 | °C | 3 | ||
| Input rise and fall times | dt/dv | 0 | 100 | ns/V | VCC = 3.3 ± 0.3 V | 3 | |
| Input rise and fall times | dt/dv | 0 | 20 | ns/V | VCC = 5.0 ± 0.5 V | 3 | |
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 3 |
CAD (KiCad official)
- Symbol:
74VHC00FT - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74vhc00ft-etched.step/74vhc00ft-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74vhc00ft.step/74vhc00ft.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (7 pp, sha256
faa861279edd6196, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).