component

74LVTH244APW

Public Made by Adom

by adom

Nexperia Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic ics74lvth244apwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
74lvth244apw / README.md
History Download
Ray Publish 0.1.0 0a8d82d 13d ago

74LVTH244APW

Nexperia · Logic ICs · TSSOP-20

74LVTH244APW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input (active low) for outputs 1Y0 to 1Y3; a HIGH forces those outputs to the high-impedance OFF-state.
2 1A0 input Data input 1A0 of the first 4-bit buffer; bus hold input with overvoltage-tolerant inputs to 5.5 V.
3 2Y3 tri_state 3-state data output 2Y3 of the second 4-bit buffer; high-impedance when 2OE is HIGH.
4 1A1 input Data input 1A1 of the first 4-bit buffer; bus hold input with overvoltage-tolerant inputs to 5.5 V.
5 2Y2 tri_state 3-state data output 2Y2 of the second 4-bit buffer; high-impedance when 2OE is HIGH.
6 1A2 input Data input 1A2 of the first 4-bit buffer; bus hold input with overvoltage-tolerant inputs to 5.5 V.
7 2Y1 tri_state 3-state data output 2Y1 of the second 4-bit buffer; high-impedance when 2OE is HIGH.
8 1A3 input Data input 1A3 of the first 4-bit buffer; bus hold input with overvoltage-tolerant inputs to 5.5 V.
9 2Y0 tri_state 3-state data output 2Y0 of the second 4-bit buffer; high-impedance when 2OE is HIGH.
10 GND power_in Ground (0 V) reference pin.
11 2A0 input Data input 2A0 of the second 4-bit buffer; bus hold input with overvoltage-tolerant inputs to 5.5 V.
12 1Y3 tri_state 3-state data output 1Y3 of the first 4-bit buffer; high-impedance when 1OE is HIGH.
13 2A1 input Data input 2A1 of the second 4-bit buffer; bus hold input with overvoltage-tolerant inputs to 5.5 V.
14 1Y2 tri_state 3-state data output 1Y2 of the first 4-bit buffer; high-impedance when 1OE is HIGH.
15 2A2 input Data input 2A2 of the second 4-bit buffer; bus hold input with overvoltage-tolerant inputs to 5.5 V.
16 1Y1 tri_state 3-state data output 1Y1 of the first 4-bit buffer; high-impedance when 1OE is HIGH.
17 2A3 input Data input 2A3 of the second 4-bit buffer; bus hold input with overvoltage-tolerant inputs to 5.5 V.
18 1Y0 tri_state 3-state data output 1Y0 of the first 4-bit buffer; high-impedance when 1OE is HIGH.
19 2OE input Output enable input (active low) for outputs 2Y0 to 2Y3; a HIGH forces those outputs to the high-impedance OFF-state.
20 VCC power_in Supply voltage, specified from 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 4.6 V 4
input voltage VI -0.5 7 V 4
output voltage VO -0.5 7 V output in OFF-state or HIGH-state 4
input clamping current IIK -50 mA VI < 0 V 4
output clamping current IOK -50 mA VO < 0 V 4
output current IO 128 mA output in LOW-state 4
output current IO -64 mA output in HIGH-state 4
storage temperature Tstg -65 150 °C 4
junction temperature Tj 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 to +85 °C 4
supply voltage VCC 2.7 3.6 V 4
input voltage VI 0 5.5 V 4
HIGH-level output current IOH -32 mA 4
LOW-level output current IOL 32 mA none 4
LOW-level output current IOL 64 mA current duty cycle ≤ 50 %; fi ≥ 1 kHz 4
ambient temperature Tamb -40 85 °C in free-air 4
input transition rise and fall rate Δt/ΔV 10 ns/V outputs enabled 4
input clamping voltage VIK -1.2 -0.9 V VCC = 2.7 V; IIK = -18 mA 5
HIGH-level input voltage VIH 2 V 5
LOW-level input voltage VIL 0.8 V 5
HIGH-level output voltage VOH 2.4 2.5 V VCC = 2.7 V to 3.6 V; IOH = -8 mA 5
HIGH-level output voltage VOH 2 2.2 V VCC = 3.0 V; IOH = -32 mA 5
LOW-level output voltage VOL 0.1 0.2 V VCC = 2.7 V; IOL = 100 μA 5
LOW-level output voltage VOL 0.3 0.5 V VCC = 2.7 V; IOL = 24 mA 5
LOW-level output voltage VOL 0.25 0.4 V VCC = 3.0 V; IOL = 16 mA 5
LOW-level output voltage VOL 0.4 0.55 V VCC = 3.0 V; IOL = 64 mA 5
input leakage current (all input pins) II 0.1 10 μA all input pins; VCC = 0 V or 3.6 V; VI = 5.5 V 5
input leakage current (control pins) II -1 0.1 1 μA control pins; VCC = 3.6 V; VI = VCC or GND 5
input leakage current (data pins) II 0.1 1 μA data pins; VCC = 3.6 V; VI = VCC 5
input leakage current II -5 -1 μA VCC = 3.6 V; VI = 0 V 5
power-off leakage current IOFF -100 1 100 μA VCC = 0 V; VI or VO = 0 V to 4.5 V 5
bus hold LOW current IBHL 75 150 μA VCC = 3 V; VI = 0.8 V 5
bus hold HIGH current IBHH -150 -75 μA VCC = 3 V; VI = 2.0 V 5
bus hold LOW overdrive current IBHLO 500 μA nAn input; VCC = 3.6 V; VI = 0 V to 3.6 V 5
bus hold HIGH overdrive current IBHHO -500 μA nAn input; VCC = 3.6 V; VI = 0 V to 3.6 V 5
external current IEX 60 125 μA nYn output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V 5
power-up/power-down output current IO(pu/pd) -100 1 100 μA VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don't care 5
OFF-state output current IOZ 1 5 μA VCC = 3.6 V; VI = VIH or VIL; VO = 3.0 V 5
OFF-state output current IOZ -5 -1 μA VCC = 3.6 V; VI = VIH or VIL; VO = 0.5 V 5
supply current (output HIGH) ICC 0.13 0.19 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A; output HIGH 5
supply current (output LOW) ICC 3 12 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A; output LOW 5
supply current (outputs disabled) ICC 0.13 0.19 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A; outputs disabled 5
additional supply current per input pin ΔICC 0.1 0.2 mA VCC = 3.0 V to 3.6 V; one input at VCC - 0.6 V and other inputs at VCC or GND 5
LOW to HIGH propagation delay tPLH 5 ns nAn to nYn; see Fig. 3; VCC = 2.7 V 6
LOW to HIGH propagation delay tPLH 1 2.5 4.1 ns nAn to nYn; see Fig. 3; VCC = 3.0 V to 3.6 V 6
HIGH to LOW propagation delay tPHL 5.1 ns nAn to nYn; see Fig. 3; VCC = 2.7 V 6
HIGH to LOW propagation delay tPHL 1 2.6 4.1 ns nAn to nYn; see Fig. 3; VCC = 3.0 V to 3.6 V 6
OFF-state to HIGH propagation delay tPZH 6.3 ns nOE to nYn; see Fig. 4; VCC = 2.7 V 6
OFF-state to HIGH propagation delay tPZH 1 3.2 5.2 ns nOE to nYn; see Fig. 4; VCC = 3.0 V to 3.6 V 6
OFF-state to LOW propagation delay tPZL 6.7 ns nOE to nYn; see Fig. 4; VCC = 2.7 V 6
OFF-state to LOW propagation delay tPZL 1.1 3.1 5.2 ns nOE to nYn; see Fig. 4; VCC = 3.0 V to 3.6 V 6
HIGH to OFF-state propagation delay tPHZ 6.3 ns nOE to nYn; see Fig. 4; VCC = 2.7 V 6
HIGH to OFF-state propagation delay tPHZ 1.9 3.3 5.6 ns nOE to nYn; see Fig. 4; VCC = 3.0 V to 3.6 V 6
LOW to OFF-state propagation delay tPLZ 5.6 ns nOE to nYn; see Fig. 4; VCC = 2.7 V 6
LOW to OFF-state propagation delay tPLZ 1.8 3.3 5.1 ns nOE to nYn; see Fig. 4; VCC = 3.0 V to 3.6 V 6

CAD (KiCad official)

  • Symbol: 74LVTH244APW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lvth244apw-etched.step / 74lvth244apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvth244apw.step / 74lvth244apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 766604675ad5fb7a, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF