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74LVT573PW

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Nexperia Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVT573PW

Nexperia · Logic ICs · TSSOP-20

74LVT573PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable input, active LOW; a HIGH on OE forces the outputs into the high-impedance OFF-state without changing the latch contents.
2 D0 input Data input 0; recommended input voltage range is 0 V to 5.5 V and the input has bus hold.
3 D1 input Data input 1; recommended input voltage range is 0 V to 5.5 V and the input has bus hold.
4 D2 input Data input 2; recommended input voltage range is 0 V to 5.5 V and the input has bus hold.
5 D3 input Data input 3; recommended input voltage range is 0 V to 5.5 V and the input has bus hold.
6 D4 input Data input 4; recommended input voltage range is 0 V to 5.5 V and the input has bus hold.
7 D5 input Data input 5; recommended input voltage range is 0 V to 5.5 V and the input has bus hold.
8 D6 input Data input 6; recommended input voltage range is 0 V to 5.5 V and the input has bus hold.
9 D7 input Data input 7; recommended input voltage range is 0 V to 5.5 V and the input has bus hold.
10 GND power_in Ground (0 V) reference for all voltages.
11 LE input Latch enable input, active HIGH; when HIGH the latches are transparent, and the data is stored on the HIGH-to-LOW transition of LE.
12 Q7 tri_state Data output 7, 3-state; high-impedance when OE is HIGH, with IOL up to 32 mA and IOH down to -32 mA recommended.
13 Q6 tri_state Data output 6, 3-state; high-impedance when OE is HIGH, with IOL up to 32 mA and IOH down to -32 mA recommended.
14 Q5 tri_state Data output 5, 3-state; high-impedance when OE is HIGH, with IOL up to 32 mA and IOH down to -32 mA recommended.
15 Q4 tri_state Data output 4, 3-state; high-impedance when OE is HIGH, with IOL up to 32 mA and IOH down to -32 mA recommended.
16 Q3 tri_state Data output 3, 3-state; high-impedance when OE is HIGH, with IOL up to 32 mA and IOH down to -32 mA recommended.
17 Q2 tri_state Data output 2, 3-state; high-impedance when OE is HIGH, with IOL up to 32 mA and IOH down to -32 mA recommended.
18 Q1 tri_state Data output 1, 3-state; high-impedance when OE is HIGH, with IOL up to 32 mA and IOH down to -32 mA recommended.
19 Q0 tri_state Data output 0, 3-state; high-impedance when OE is HIGH, with IOL up to 32 mA and IOH down to -32 mA recommended.
20 VCC power_in Supply voltage, recommended range 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 4.6 V 4
Input voltage VI -0.5 7 V 4
Output voltage VO -0.5 7 V output in OFF-state or HIGH-state 4
Input clamping current IIK -50 mA VI < 0 V 4
Output clamping current IOK -50 mA VO < 0 V 4
Output current IO 128 mA output in LOW-state 4
Output current IO -64 mA output in HIGH-state 4
Storage temperature Tstg -65 150 °C 4
Junction temperature Tj 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +85 °C 4
Supply voltage VCC 2.7 3.6 V 5
Input voltage VI 0 5.5 V 5
HIGH-level input voltage VIH 2 V 5
LOW-level input voltage VIL 0.8 V 5
HIGH-level output current IOH -32 mA 5
LOW-level output current IOL 32 mA 5
Output current (pulsed) 64 mA current duty cycle ≤ 50 %; fi ≥ 1 kHz 5
Ambient temperature Tamb -40 85 °C in free air 5
Input transition rise and fall rate Δt/ΔV 10 ns/V outputs enabled 5
Input clamping voltage VIK -1.2 -0.9 V VCC = 2.7 V; IIK = -18 mA 5
HIGH-level output voltage VOH 2.4 2.5 V VCC = 2.7 V; IOH = -8 mA 5
HIGH-level output voltage VOH 2 2.2 V VCC = 3.0 V; IOH = -32 mA 5
LOW-level output voltage VOL 0.3 0.5 V VCC = 2.7 V; IOL = 24 mA 5
LOW-level output voltage VOL 0.4 0.55 V VCC = 3.0 V; IOL = 64 mA 5
Power-up LOW-level output voltage VOL(pu) 0.13 0.55 V VCC = 3.6 V; IO = 1 mA; VI = GND or VCC 5
Input leakage current (all input pins) II 1 10 μA VCC = 0 V or 3.6 V; VI = 5.5 V 5
Input leakage current (data pins) II 0.1 1 μA VCC = 3.6 V; VI = VCC 5
Input leakage current II -5 -1 μA VCC = 3.6 V; VI = 0 V 5
Power-off leakage current IOFF -100 1 100 μA VCC = 0 V; VI or VO = 0 V to 4.5 V 5
Bus hold LOW current IBHL 75 150 μA Dn input; VCC = 3 V; VI = 0.8 V 5
Bus hold HIGH current IBHH -150 -75 μA Dn input; VCC = 3 V; VI = 2.0 V 5
Bus hold HIGH overdrive current IBHHO 500 μA Dn input; VCC = 3.6 V; VI = 0 V to 3.6 V 5
Bus hold LOW overdrive current IBHLO -500 μA Dn input; VCC = 3.6 V; VI = 0 V to 3.6 V 5
Output leakage current ILO 60 125 μA Qn output HIGH when VO = 5.5 V and VCC = 3.0 V 6
OFF-state output current (HIGH) IOZ 1 5 μA VCC = 3.6 V; VI = VIH or VIL; VO = 3.0 V 6
Supply current (outputs HIGH) ICC 0.13 0.19 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A 6
Supply current (outputs LOW) ICC 3 12 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A 6
Additional supply current per input pin ΔICC 0.1 0.2 mA VCC = 3 V to 3.6 V; one input at VCC - 0.6 V and other inputs at VCC or GND 6
LE to Qn propagation delay, LOW to HIGH tPLH 1.6 3.5 5.6 ns VCC = 3.0 V to 3.6 V; see Fig. 4 7
LE to Qn propagation delay, LOW to HIGH tPLH 6.3 ns VCC = 2.7 V; see Fig. 4 7
Dn to Qn propagation delay, LOW to HIGH tPLH 1 2.5 4.2 ns VCC = 3.0 V to 3.6 V; see Fig. 5 7
Dn to Qn propagation delay, LOW to HIGH tPLH 4.7 ns VCC = 2.7 V; see Fig. 5 7
LE to Qn propagation delay, HIGH to LOW tPHL 2.5 4.3 6.5 ns VCC = 3.0 V to 3.6 V; see Fig. 4 7
LE to Qn propagation delay, HIGH to LOW tPHL 7.2 ns VCC = 2.7 V; see Fig. 4 7
Dn to Qn propagation delay, HIGH to LOW tPHL 1 2.7 4.3 ns VCC = 3.0 V to 3.6 V; see Fig. 5 7
Dn to Qn propagation delay, HIGH to LOW tPHL 5.2 ns VCC = 2.7 V; see Fig. 5 7
OFF-state to HIGH propagation delay tPZH 1 2.8 5.1 ns VCC = 3.0 V to 3.6 V; see Fig. 6 7
OFF-state to HIGH propagation delay tPZH 6.2 ns VCC = 2.7 V; see Fig. 6 7
OFF-state to LOW propagation delay tPZL 1.3 3.3 5.5 ns VCC = 3.0 V to 3.6 V; see Fig. 7 7
OFF-state to LOW propagation delay tPZL 6.6 ns VCC = 2.7 V; see Fig. 7 7
HIGH to OFF-state propagation delay tPHZ 2 3.7 5.7 ns VCC = 3.0 V to 3.6 V; see Fig. 6 7
HIGH to OFF-state propagation delay tPHZ 6.7 ns VCC = 2.7 V; see Fig. 6 7
LOW to OFF-state propagation delay tPLZ 1.5 3 4.6 ns VCC = 3.0 V to 3.6 V; see Fig. 7 7
LOW to OFF-state propagation delay tPLZ 5.1 ns VCC = 2.7 V; see Fig. 7 7
Set-up time Dn to LE tsu 0.7 ns VCC = 3.0 V to 3.6 V; see Fig. 8 7
Set-up time Dn to LE tsu 0.6 ns VCC = 2.7 V; see Fig. 8 7
Hold time Dn to LE th 1.6 ns VCC = 3.0 V to 3.6 V; see Fig. 8 7
Hold time Dn to LE th 1.8 ns VCC = 2.7 V; see Fig. 8 7
LE pulse width HIGH tW 3.3 ns VCC = 3.0 V to 3.6 V; see Fig. 4 7

CAD (KiCad official)

  • Symbol: 74LVT573PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lvt573pw-etched.step / 74lvt573pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvt573pw.step / 74lvt573pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 b34f18f2a87aa587, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF