74LVT2244PW

{
  "schema_version": 1,
  "type": "component",
  "slug": "74lvt2244pw",
  "title": "74LVT2244PW",
  "brief": "Nexperia Global Sourcing Parts, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "global sourcing parts",
    "74lvt2244pw"
  ],
  "component": {
    "mpn": "74LVT2244PW",
    "manufacturer": "Nexperia",
    "package": "TSSOP-20",
    "pin_count": 20,
    "category": "Global Sourcing Parts",
    "subcategory": "Global Sourcing Parts",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586171371047436288",
    "parts": {
      "symbol": "74lvt2244pw.kicad_sym",
      "footprint": "74lvt2244pw.kicad_mod",
      "model_3d": "74lvt2244pw-etched.glb",
      "model_3d_plain": "74lvt2244pw.glb",
      "model_3d_step": "74lvt2244pw-etched.step",
      "model_3d_step_plain": "74lvt2244pw.step",
      "lbr": "74lvt2244pw.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1OE",
        "type": "input",
        "description": "Active-LOW output enable for bank 1 (outputs 1Y0-1Y3). LOW = outputs driven from 1A0-1A3; HIGH = outputs in high-impedance (Z) state. VIH ≥ 2.0 V, VIL ≤ 0.8 V."
      },
      {
        "number": "2",
        "name": "1A0",
        "type": "input",
        "description": "Bank 1 data input, channel 0. TTL-compatible logic input with bus-hold; drives 1Y0 when 1OE is LOW. Overvoltage-tolerant to 5.5 V."
      },
      {
        "number": "3",
        "name": "2Y3",
        "type": "tri_state",
        "description": "Bank 2 data output, channel 3. 3-state buffered copy of 2A3 with ~30 Ω integrated series termination. IOH = -12 mA, IOL = +12 mA. High-Z when 2OE is HIGH."
      },
      {
        "number": "4",
        "name": "1A1",
        "type": "input",
        "description": "Bank 1 data input, channel 1. TTL-compatible logic input with bus-hold; drives 1Y1 when 1OE is LOW. Overvoltage-tolerant to 5.5 V."
      },
      {
        "number": "5",
        "name": "2Y2",
        "type": "tri_state",
        "description": "Bank 2 data output, channel 2. 3-state buffered copy of 2A2 with ~30 Ω integrated series termination. IOH = -12 mA, IOL = +12 mA. High-Z when 2OE is HIGH."
      },
      {
        "number": "6",
        "name": "1A2",
        "type": "input",
        "description": "Bank 1 data input, channel 2. TTL-compatible logic input with bus-hold; drives 1Y2 when 1OE is LOW. Overvoltage-tolerant to 5.5 V."
      },
      {
        "number": "7",
        "name": "2Y1",
        "type": "tri_state",
        "description": "Bank 2 data output, channel 1. 3-state buffered copy of 2A1 with ~30 Ω integrated series termination. IOH = -12 mA, IOL = +12 mA. High-Z when 2OE is HIGH."
      },
      {
        "number": "8",
        "name": "1A3",
        "type": "input",
        "description": "Bank 1 data input, channel 3. TTL-compatible logic input with bus-hold; drives 1Y3 when 1OE is LOW. Overvoltage-tolerant to 5.5 V."
      },
      {
        "number": "9",
        "name": "2Y0",
        "type": "tri_state",
        "description": "Bank 2 data output, channel 0. 3-state buffered copy of 2A0 with ~30 Ω integrated series termination. IOH = -12 mA, IOL = +12 mA. High-Z when 2OE is HIGH."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Ground (0 V) reference for the device. Connect to system ground with a low-inductance path."
      },
      {
        "number": "11",
        "name": "2A0",
        "type": "input",
        "description": "Bank 2 data input, channel 0. TTL-compatible logic input with bus-hold; drives 2Y0 when 2OE is LOW. Overvoltage-tolerant to 5.5 V."
      },
      {
        "number": "12",
        "name": "1Y3",
        "type": "tri_state",
        "description": "Bank 1 data output, channel 3. 3-state buffered copy of 1A3 with ~30 Ω integrated series termination. IOH = -12 mA, IOL = +12 mA. High-Z when 1OE is HIGH."
      },
      {
        "number": "13",
        "name": "2A1",
        "type": "input",
        "description": "Bank 2 data input, channel 1. TTL-compatible logic input with bus-hold; drives 2Y1 when 2OE is LOW. Overvoltage-tolerant to 5.5 V."
      },
      {
        "number": "14",
        "name": "1Y2",
        "type": "tri_state",
        "description": "Bank 1 data output, channel 2. 3-state buffered copy of 1A2 with ~30 Ω integrated series termination. IOH = -12 mA, IOL = +12 mA. High-Z when 1OE is HIGH."
      },
      {
        "number": "15",
        "name": "2A2",
        "type": "input",
        "description": "Bank 2 data input, channel 2. TTL-compatible logic input with bus-hold; drives 2Y2 when 2OE is LOW. Overvoltage-tolerant to 5.5 V."
      },
      {
        "number": "16",
        "name": "1Y1",
        "type": "tri_state",
        "description": "Bank 1 data output, channel 1. 3-state buffered copy of 1A1 with ~30 Ω integrated series termination. IOH = -12 mA, IOL = +12 mA. High-Z when 1OE is HIGH."
      },
      {
        "number": "17",
        "name": "2A3",
        "type": "input",
        "description": "Bank 2 data input, channel 3. TTL-compatible logic input with bus-hold; drives 2Y3 when 2OE is LOW. Overvoltage-tolerant to 5.5 V."
      },
      {
        "number": "18",
        "name": "1Y0",
        "type": "tri_state",
        "description": "Bank 1 data output, channel 0. 3-state buffered copy of 1A0 with ~30 Ω integrated series termination. IOH = -12 mA, IOL = +12 mA. High-Z when 1OE is HIGH."
      },
      {
        "number": "19",
        "name": "2OE",
        "type": "input",
        "description": "Active-LOW output enable for bank 2 (outputs 2Y0-2Y3). LOW = outputs driven from 2A0-2A3; HIGH = outputs in high-impedance (Z) state. VIH ≥ 2.0 V, VIL ≤ 0.8 V."
      },
      {
        "number": "20",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage input. Operating range 2.7 V to 3.6 V (absolute max +4.6 V). Decouple locally with a 100 nF ceramic capacitor to GND."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586171371047436288",
        "pages": 13,
        "sha256": "f3ba84a19dfdef6e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74LVT2244",
      "logic_family": "74LVT",
      "function_code": "2244",
      "function_class": null,
      "function_name": null,
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "74lvt2244pw.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          6.5,
          1.2
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74lvt2244pw-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          6.5,
          1.2
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "e375e0db56dc77e21a3f918b07b206c68695145747846295284f9cd07b8d5f68",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Nexperia",
      "Package": "TSSOP-20",
      "Category": "Global Sourcing Parts",
      "Pins": "20"
    }
  },
  "variants": [
    {
      "mpn": "74LVT2244PW",
      "kind": "packaging"
    },
    {
      "mpn": "74LVT2244PWD",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "74lvt2244pw"
  ],
  "discovery_pitch": "74LVT2244PW (Nexperia) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "74lvt2244pw.kicad_sym",
    "74lvt2244pw.kicad_mod",
    "74lvt2244pw.glb",
    "74lvt2244pw.step",
    "74lvt2244pw.lbr",
    "docs/hero.png",
    "docs/74lvt2244pw-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T15:17:30.205Z"
}