# 74LVCH2T45DC

**Nexperia** · Translators, Level Shifters · VSSOP-8-0.5mm

74LVCH2T45DC from Nexperia, in a VSSOP-8-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC(A) | power_in | Supply voltage for port A and DIR, specified from 1.2 V to 5.5 V. |
| 2 | 1A | bidirectional | Data input or output referenced to VCC(A); inputs accept up to 5.5 V and the port goes high-impedance when either supply is at GND level (suspend mode). |
| 3 | 2A | bidirectional | Data input or output referenced to VCC(A); inputs accept up to 5.5 V and the port goes high-impedance when either supply is at GND level (suspend mode). |
| 4 | GND | power_in | Ground reference at 0 V for the device. |
| 5 | DIR | input | Direction control referenced to VCC(A); HIGH allows transmission from nA to nB and LOW allows transmission from nB to nA. |
| 6 | 2B | bidirectional | Data input or output referenced to VCC(B); inputs accept up to 5.5 V and the port goes high-impedance when either supply is at GND level (suspend mode). |
| 7 | 1B | bidirectional | Data input or output referenced to VCC(B); inputs accept up to 5.5 V and the port goes high-impedance when either supply is at GND level (suspend mode). |
| 8 | VCC(B) | power_in | Supply voltage for port B, specified from 1.2 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | VSSOP-8-0.5mm |
| Category | Logic |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC(A) supply voltage A | VCC(A) | -0.5 |  | 6.5 | V |  | 4 |
| VCC(B) supply voltage B | VCC(B) | -0.5 |  | 6.5 | V |  | 4 |
| input clamping current | IIK | -50 |  |  | mA | VI < 0 V | 4 |
| input voltage | VI | -0.5 |  | 6.5 | V |  | 4 |
| output clamping current | IOK | -50 |  |  | mA | VO < 0 V | 4 |
| output voltage, suspend or 3-state mode | VO | -0.5 |  | 6.5 | V | Suspend or 3-state mode | 4 |
| output current | IO | -50 |  | 50 | mA | VO = 0 V to VCCO | 4 |
| supply current | ICC |  |  | 100 | mA | ICC(A) or ICC(B) | 4 |
| ground current | IGND | -100 |  |  | mA |  | 4 |
| storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| total power dissipation | Ptot |  |  | 250 | mW | Tamb = -40 °C to +125 °C | 4 |
| VCC(A) supply voltage A | VCC(A) | 1.2 |  | 5.5 | V |  | 5 |
| VCC(B) supply voltage B | VCC(B) | 1.2 |  | 5.5 | V |  | 5 |
| input voltage | VI | 0 |  | 5.5 | V |  | 5 |
| output voltage | VO | 0 |  | 5.5 | V | Suspend or 3-state mode | 5 |
| ambient temperature | Tamb | -40 |  | 125 | °C |  | 5 |
| input transition rise and fall rate | Δt/ΔV |  |  | 20 | ns/V | VCCI = 1.2 V | 5 |
| input transition rise and fall rate | Δt/ΔV |  |  | 10 | ns/V | VCCI = 3 V to 3.6 V | 5 |
| input transition rise and fall rate | Δt/ΔV |  |  | 5 | ns/V | VCCI = 4.5 V to 5.5 V | 5 |
| HIGH-level input voltage, data input | VIH | 1.7 |  |  | V | data input; VCCI = 2.3 V to 2.7 V | 6 |
| HIGH-level input voltage, data input | VIH | 2 |  |  | V | data input; VCCI = 3.0 V to 3.6 V | 6 |
| HIGH-level input voltage, DIR input | VIH | 1.7 |  |  | V | DIR input; VCCI = 2.3 V to 2.7 V | 6 |
| HIGH-level input voltage, DIR input | VIH | 2 |  |  | V | DIR input; VCCI = 3.0 V to 3.6 V | 6 |
| LOW-level input voltage, data input | VIL |  |  | 0.7 | V | data input; VCCI = 2.3 V to 2.7 V | 6 |
| LOW-level input voltage, data input | VIL |  |  | 0.8 | V | data input; VCCI = 3.0 V to 3.6 V | 6 |
| LOW-level input voltage, DIR input | VIL |  |  | 0.7 | V | DIR input; VCCI = 2.3 V to 2.7 V | 6 |
| LOW-level input voltage, DIR input | VIL |  |  | 0.8 | V | DIR input; VCCI = 3.0 V to 3.6 V | 6 |
| HIGH-level output voltage | VOH | 1 |  |  | V | IO = -6 mA; VCCO = 1.4 V | 6 |
| HIGH-level output voltage | VOH | 1.2 |  |  | V | IO = -8 mA; VCCO = 1.65 V | 6 |
| HIGH-level output voltage | VOH | 1.9 |  |  | V | IO = -12 mA; VCCO = 2.3 V | 6 |
| HIGH-level output voltage | VOH | 2.4 |  |  | V | IO = -24 mA; VCCO = 3.0 V | 6 |
| HIGH-level output voltage | VOH | 3.8 |  |  | V | IO = -32 mA; VCCO = 4.5 V | 6 |
| LOW-level output voltage | VOL |  |  | 0.1 | V | IO = 100 μA; VCCO = 1.2 V to 4.5 V | 6 |
| LOW-level output voltage | VOL |  |  | 0.3 | V | IO = 6 mA; VCCO = 1.4 V | 6 |
| LOW-level output voltage | VOL |  |  | 0.45 | V | IO = 8 mA; VCCO = 1.65 V | 6 |
| LOW-level output voltage | VOL |  |  | 0.55 | V | IO = 24 mA; VCCO = 3.0 V | 6 |
| input leakage current, DIR input | II | -10 |  | 10 | μA | DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V | 7 |
| bus hold LOW current, A or B port | IBHL | 10 |  |  | μA | A or B port; VI = 0.49 V; VCCI = 1.4 V | 7 |
| bus hold LOW current, A or B port | IBHL | 20 |  |  | μA | A or B port; VI = 0.58 V; VCCI = 1.65 V | 7 |
| bus hold LOW current, A or B port | IBHL | 45 |  |  | μA | A or B port; VI = 0.70 V; VCCI = 2.3 V | 7 |
| bus hold LOW current, A or B port | IBHL | 80 |  |  | μA | A or B port; VI = 0.80 V; VCCI = 3.0 V | 7 |
| bus hold LOW current, A or B port | IBHL | 100 |  |  | μA | A or B port; VI = 1.35 V; VCCI = 4.5 V | 7 |
| bus hold HIGH current, A or B port | IBHH | -10 |  |  | μA | A or B port; VI = 0.91 V; VCCI = 1.4 V | 7 |
| bus hold HIGH current, A or B port | IBHH | -20 |  |  | μA | A or B port; VI = 1.07 V; VCCI = 1.65 V | 7 |
| bus hold HIGH current, A or B port | IBHH | -45 |  |  | μA | A or B port; VI = 1.60 V; VCCI = 2.3 V | 7 |
| bus hold HIGH current, A or B port | IBHH | -80 |  |  | μA | A or B port; VI = 2.00 V; VCCI = 3.0 V | 7 |
| bus hold HIGH current, A or B port | IBHH | -100 |  |  | μA | A or B port; VI = 3.15 V; VCCI = 4.5 V | 7 |
| OFF-state output current | IOZ | -10 |  | 10 | μA | A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V | 7 |
| power-off leakage current, A port | IOFF | -10 |  | 10 | μA | A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V | 7 |
| power-off leakage current, B port | IOFF | -10 |  | 10 | μA | B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V | 7 |
| supply current, A plus B port (ICC(A) + ICC(B)) | ICC |  |  | 16 | μA | IO = 0 A; VI = 0 V or VCCI; VCC(A), VCC(B) = 1.2 V to 5.5 V | 8 |
| supply current, A plus B port (ICC(A) + ICC(B)) | ICC |  |  | 4 | μA | IO = 0 A; VI = 0 V or VCCI; VCC(A), VCC(B) = 1.65 V to 5.5 V | 8 |

## CAD (KiCad official)

- Symbol: `74LVCH2T45DC`
- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`
- 3D model: VSSOP-8-0.5mm (KiCad packages3D, STEP)
- 3D model files: `74lvch2t45dc-etched.step` / `74lvch2t45dc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvch2t45dc.step` / `74lvch2t45dc.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913549393870848) (33 pp, sha256 `9c2671f306ce6dc0`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lvch2t45dc-datasheet.pdf)