component
74LVCE1G86W5-7
Public Made by Adomby adom
Diodes Incorporated Logic Gates, SOT-25-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LVCE1G86W5-7
Diodes Incorporated · Logic Gates · SOT-25-5
74LVCE1G86W5-7 from Diodes Incorporated, in a SOT-25-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Data input A of the EXCLUSIVE OR gate, tolerant of input voltages up to 5.5V. |
| 2 | B | input | Data input B of the EXCLUSIVE OR gate, tolerant of input voltages up to 5.5V. |
| 3 | GND | power_in | Ground. |
| 4 | Y | output | Data output with a standard totem pole stage, driving ±24mA at 3.3V and disabled by the IOFF circuitry when the device is powered down. |
| 5 | Vcc | power_in | Supply voltage, operating range 1.4V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-25-5 |
| Category | Logic |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input low-level voltage | VIL | 0.35 | x VCC | VCC = 1.4 V to 1.95 V | 4 | ||
| Input low-level voltage | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| Input low-level voltage | VIL | 0.8 | V | VCC = 3 V to 3.6 V | 4 | ||
| Input low-level voltage | VIL | 0.3 | x VCC | VCC = 4.5 V to 5.5 V | 4 | ||
| High-level input voltage | VIH | 0.65 | x VCC | VCC = 1.4 V to 1.95 V | 4 | ||
| High-level input voltage | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| High-level input voltage | VIH | 2 | V | VCC = 3 V to 3.6 V | 4 | ||
| High-level input voltage | VIH | 0.7 | x VCC | VCC = 4.5 V to 5.5 V | 4 | ||
| Operating voltage | VCC | 1.4 | 5.5 | V | Operating | 4 | |
| Data retention voltage | VCC | 1.2 | V | Data retention only | 4 | ||
| Input voltage | VI | 0 | 5.5 | V | 4 | ||
| High-level output current | IOH | -8 | mA | VCC = 2.3 V | 4 | ||
| High-level output current | IOH | -16 | mA | VCC = 3 V | 4 | ||
| High-level output current | IOH | -32 | mA | VCC = 4.5 V | 4 | ||
| Low-level output current | IOL | 8 | mA | VCC = 2.3 V | 4 | ||
| Low-level output current | IOL | 16 | mA | VCC = 3 V | 4 | ||
| Low-level output current | IOL | 32 | mA | VCC = 4.5 V | 4 | ||
| Input transition rise or fall rate | Δt/ΔV | 20 | ns/V | VCC = 1.4 to 3 V | 4 | ||
| Input transition rise or fall rate | Δt/ΔV | 10 | ns/V | VCC = 3.3 V ± 0.3 V | 4 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| ESD Human Body Model protection | ESD HBM | 2 | kV | Human Body Model | 3 | ||
| ESD Machine Model protection | ESD MM | 200 | V | Machine Model | 3 | ||
| Supply voltage range | VCC | -0.5 | 6.5 | V | 3 | ||
| Input voltage range | VI | -0.5 | 6.5 | V | 3 | ||
| Voltage applied to output in high impedance or IOFF state | Vo | -0.5 | 6.5 | V | High impedance or IOFF state | 3 | |
| Voltage applied to output in high or low state | Vo | -0.3 | V | High or low state; upper limit is VCC + 0.5 V as printed | 3 | ||
| Continuous output current | IO | -50 | 50 | mA | 3 | ||
| Continuous current through VDD or GND | -100 | 100 | mA | 3 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 3 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 3 | ||
| Thermal resistance junction-to-ambient, SOT25 | θJA | 204 | °C/W | SOT25; test per Note 5 (FR-4 PCB, 2 oz copper, minimum recommended pad layout) | 5 | ||
| Thermal resistance junction-to-case, SOT25 | θJC | 52 | °C/W | SOT25; test per Note 5 (FR-4 PCB, 2 oz copper, minimum recommended pad layout) | 5 | ||
| High level output voltage | VOH | 1.05 | V | IOH = -3 mA, VCC = 1.4 V | 5 | ||
| High level output voltage | VOH | 1.2 | V | IOH = -4 mA, VCC = 1.65 V | 5 | ||
| High level output voltage | VOH | 1.9 | V | IOH = -8 mA, VCC = 2.3 V | 5 | ||
| High level output voltage | VOH | 2.4 | V | IOH = -16 mA, VCC = 3 V | 5 | ||
| High level output voltage | VOH | 2.3 | V | IOH = -24 mA (VCC not printed on row) | 5 | ||
| High level output voltage | VOH | 3.8 | V | IOH = -32 mA, VCC = 4.5 V | 5 | ||
| Low level output voltage | VOL | 0.1 | V | IOL = 100 μA, VCC = 1.4 V to 5.5 V | 5 | ||
| Low level output voltage | VOL | 0.4 | V | IOL = 3 mA, VCC = 1.4 V | 5 | ||
| Low level output voltage | VOL | 0.45 | V | IOL = 4 mA, VCC = 1.65 V | 5 | ||
| Low level output voltage | VOL | 0.3 | V | IOL = 8 mA, VCC = 2.3 V | 5 | ||
| Low level output voltage | VOL | 0.55 | V | IOL = 24 mA (VCC not printed on row) | 5 | ||
| Input current | II | -5 | 5 | μA | VI = 5.5 V or GND, VCC = 0 to 5.5 V | 5 | |
| Power down leakage current | IOFF | -10 | 10 | μA | VI or VO = 5.5 V, VCC = 0 | 5 | |
| Supply current | ICC | 10 | μA | VI = 5.5 V or GND, IO = 0, VCC = 1.4 V to 5.5 V | 5 | ||
| Additional supply current | ΔICC | 500 | μA | One input at VCC - 0.6 V, other inputs at VCC or GND, VCC = 3 V to 5.5 V | 5 | ||
| Input capacitance | Ci | 3.5 | pF | VI = VCC or GND, VCC = 3.3 V | 5 | ||
| Propagation delay A or B to Y | tpd | 2.1 | 9.1 | ns | CL = 15 pF, VCC = 1.5 V ± 0.1 V | 6 | |
| Propagation delay A or B to Y | tpd | 1.4 | 6.3 | ns | CL = 15 pF, VCC = 1.8 V ± 0.15 V | 6 | |
| Propagation delay A or B to Y | tpd | 0.8 | 3.6 | ns | CL = 15 pF, VCC = 2.5 V ± 0.2 V | 6 | |
| Propagation delay A or B to Y | tpd | 0.6 | 3.2 | ns | CL = 15 pF, VCC = 3.3 V ± 0.3 V | 6 | |
| Propagation delay A or B to Y | tpd | 0.7 | 2.9 | ns | CL = 15 pF, VCC = 5 V ± 0.5 V | 6 | |
| Propagation delay A or B to Y | tpd | 3.5 | 9.9 | ns | CL = 30 or 50 pF as noted, VCC = 1.5 V ± 0.1 V | 6 | |
| Propagation delay A or B to Y | tpd | 2.4 | 6.9 | ns | CL = 30 or 50 pF as noted, VCC = 1.8 V ± 0.15 V | 6 | |
| Propagation delay A or B to Y | tpd | 1.4 | 4.4 | ns | CL = 30 or 50 pF as noted, VCC = 2.5 V ± 0.2 V | 6 | |
| Propagation delay A or B to Y | tpd | 1 | 4.1 | ns | CL = 30 or 50 pF as noted, VCC = 3.3 V ± 0.3 V | 6 | |
| Propagation delay A or B to Y | tpd | 0.9 | 3.6 | ns | CL = 30 or 50 pF as noted, VCC = 5 V ± 0.5 V | 6 |
CAD (KiCad official)
- Symbol:
74LVCE1G86W5-7 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-25-5 (KiCad packages3D, STEP)
- 3D model files:
74lvce1g86w5-7-etched.step/74lvce1g86w5-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvce1g86w5-7.step/74lvce1g86w5-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (14 pp, sha256
87f266f7c2a8c94e, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).