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74LVC8T595PWJ

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Nexperia Shift Registers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC8T595PWJ

Nexperia · Shift Registers · TSSOP-20

74LVC8T595PWJ from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC(B) power_in Supply voltage B for the Qn outputs, specified from 1.1 V to 5.5 V.
2 Q0 tri_state Parallel data output Q0, referenced to VCC(B); goes high-impedance when OE is HIGH or the device is in suspend mode.
3 Q1 tri_state Parallel data output Q1, referenced to VCC(B); goes high-impedance when OE is HIGH or the device is in suspend mode.
4 Q2 tri_state Parallel data output Q2, referenced to VCC(B); goes high-impedance when OE is HIGH or the device is in suspend mode.
5 Q3 tri_state Parallel data output Q3, referenced to VCC(B); goes high-impedance when OE is HIGH or the device is in suspend mode.
6 Q4 tri_state Parallel data output Q4, referenced to VCC(B); goes high-impedance when OE is HIGH or the device is in suspend mode.
7 Q5 tri_state Parallel data output Q5, referenced to VCC(B); goes high-impedance when OE is HIGH or the device is in suspend mode.
8 Q6 tri_state Parallel data output Q6, referenced to VCC(B); goes high-impedance when OE is HIGH or the device is in suspend mode.
9 Q7 tri_state Parallel data output Q7, referenced to VCC(B); goes high-impedance when OE is HIGH or the device is in suspend mode.
10 GND power_in Ground (0 V).
11 GND power_in Ground (0 V).
12 GND power_in Ground (0 V).
13 GND power_in Ground (0 V).
14 Q7S output Serial data output referenced to VCC(A); driven LOW while MR is LOW.
15 MR input Master reset input, active LOW, referenced to VCC(A); it clears only the shift register.
16 SHCP input Shift register clock input, referenced to VCC(A); data is shifted on its positive-going transition.
17 STCP input Storage register clock input, referenced to VCC(A); the shift register contents transfer to the storage register on its positive-going transition.
18 OE input Output enable input, active LOW, referenced to VCC(A); when HIGH, the Qn outputs are forced to high-impedance.
19 DS input Serial data input, referenced to VCC(A), shifted into the shift register on the positive-going transition of SHCP.
20 VCC(A) power_in Supply voltage A for the MR, SHCP, STCP, OE, DS inputs and the Q7S output, specified from 1.1 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC(A) supply voltage A VCC(A) -0.5 6.5 V 5
VCC(B) supply voltage B VCC(B) -0.5 6.5 V 5
output current IO -50 50 mA VO = 0 V to VCCO 5
input clamping current IIK -50 mA VI < 0 V 5
output clamping current IOK -50 mA VO < 0 V 5
input voltage VI -0.5 6.5 V 5
output voltage VO -0.5 V Active mode 5
output voltage VO -0.5 6.5 V Suspend or 3-state mode 5
supply current ICC 100 mA ICC(A) or ICC(B) 5
ground current IGND -100 mA 5
storage temperature Tstg -65 150 °C 5
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
supply voltage A VCC(A) 1.1 5.5 V 6
supply voltage B VCC(B) 1.1 5.5 V 6
input voltage VI 0 5.5 V 6
output voltage VO 0 V Active mode 6
output voltage VO 0 5.5 V Suspend or 3-state mode 6
ambient temperature Tamb -40 125 °C 6
input transition rise and fall rate Δt/ΔV 20 ns/V VCC(A) = 1.1 V to 1.3 V 6
input transition rise and fall rate Δt/ΔV 10 ns/V VCC(A) = 3 V to 3.6 V 6
input transition rise and fall rate Δt/ΔV 5 ns/V VCC(A) = 4.5 V to 5.5 V 6
HIGH-level input voltage VIH 1.7 V VCC(A) = 2.3 V to 2.7 V; -40 °C to +125 °C 7
HIGH-level input voltage VIH 2 V VCC(A) = 3.0 V to 3.6 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 0.7 V VCC(A) = 2.3 V to 2.7 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 0.8 V VCC(A) = 3.0 V to 3.6 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 0.825 V VI = VIH; IO = -2 mA; VCCO = 1.1 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 1 V VI = VIH; IO = -6 mA; VCCO = 1.4 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 1.2 V VI = VIH; IO = -8 mA; VCCO = 1.65 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 1.9 V VI = VIH; IO = -12 mA; VCCO = 2.3 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 2.4 V VI = VIH; IO = -24 mA; VCCO = 3.0 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 3.85 V VI = VIH; IO = -24 mA; VCCO = 4.5 V; -40 °C to +125 °C 7
HIGH-level output voltage VOH 3.8 V VI = VIH; IO = -32 mA; VCCO = 4.5 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.1 V VI = VIL; IO = 100 μA; VCCO = 1.1 V to 4.5 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.275 V VI = VIL; IO = 2 mA; VCCO = 1.1 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.3 V VI = VIL; IO = 6 mA; VCCO = 1.4 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.45 V VI = VIL; IO = 8 mA; VCCO = 1.65 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.55 V VI = VIL; IO = 24 mA; VCCO = 3.0 V; -40 °C to +125 °C 7
LOW-level output voltage VOL 0.5 V VI = VIL; IO = 24 mA; VCCO = 4.5 V; -40 °C to +125 °C 7
input leakage current II -10 10 μA MR, SHCP, STCP, OE and DS inputs; VI = 0 V to 5.5 V; VCC(A) = 1.1 V to 5.5 V; -40 °C to +125 °C 7
OFF-state output current IOZ -10 10 μA suspend mode; VCC(A) = 0 V; VCC(B) = 5.5 V; -40 °C to +125 °C 7
power-off leakage current IOFF -10 10 μA inputs, Q7S output; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.1 V to 5.5 V; -40 °C to +125 °C 8
supply current VCC(A) domain ICC 5 μA VI = 0 V or VCC(A); IO = 0 A; VCC(A), VCC(B) = 1.1 V to 5.5 V; -40 °C to +125 °C 8
supply current VCC(A) domain ICC -2 μA VI = 0 V or VCC(A); IO = 0 A; VCC(A) = 0 V; VCC(B) = 5.5 V; -40 °C to +125 °C 8
supply current VCC(B) domain ICC 24 μA VI = 0 V or VCC(A); IO = 0 A; VCC(A), VCC(B) = 1.1 V to 5.5 V; -40 °C to +125 °C 8
supply current VCC(B) domain ICC -2 μA VI = 0 V or VCC(A); IO = 0 A; VCC(B) = 0 V; VCC(A) = 5.5 V; -40 °C to +125 °C 8
additional supply current ΔICC 75 μA per input; VCC(A), VCC(B) = 3.0 V to 5.5 V; MR, SHCP, STCP, OE inputs; one input at VCC(A) - 0.6 V; DS input at VCC(A) or GND; Qn = open; -40 °C to +125 °C 8

CAD (KiCad official)

  • Symbol: 74LVC8T595PWJ
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lvc8t595pwj-etched.step / 74lvc8t595pwj-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc8t595pwj.step / 74lvc8t595pwj.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (28 pp, sha256 2141db6e89512526, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF