component
74LVC86ABQ
Public Made by Adomby adom
Nexperia Logic Gates, DHVQFN-14(2.5x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LVC86ABQ
Nexperia · Logic Gates · DHVQFN-14(2.5x3)
74LVC86ABQ from Nexperia, in a DHVQFN-14(2.5x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1; overvoltage tolerant to 5.5 V (VI 0 to 5.5 V) with Schmitt-trigger action. |
| 2 | 1B | input | Data input of gate 1; overvoltage tolerant to 5.5 V (VI 0 to 5.5 V) with Schmitt-trigger action. |
| 3 | 1Y | output | Output of gate 1 (1Y = 1A XOR 1B); output voltage is limited to 0 V to VCC. |
| 4 | 2A | input | Data input of gate 2; overvoltage tolerant to 5.5 V (VI 0 to 5.5 V) with Schmitt-trigger action. |
| 5 | 2B | input | Data input of gate 2; overvoltage tolerant to 5.5 V (VI 0 to 5.5 V) with Schmitt-trigger action. |
| 6 | 2Y | output | Output of gate 2 (2Y = 2A XOR 2B); output voltage is limited to 0 V to VCC. |
| 7 | GND | power_in | Ground reference (0 V); all voltages in the datasheet are referenced to this pin. |
| 8 | 3Y | output | Output of gate 3 (3Y = 3A XOR 3B); output voltage is limited to 0 V to VCC. |
| 9 | 3A | input | Data input of gate 3; overvoltage tolerant to 5.5 V (VI 0 to 5.5 V) with Schmitt-trigger action. |
| 10 | 3B | input | Data input of gate 3; overvoltage tolerant to 5.5 V (VI 0 to 5.5 V) with Schmitt-trigger action. |
| 11 | 4Y | output | Output of gate 4 (4Y = 4A XOR 4B); output voltage is limited to 0 V to VCC. |
| 12 | 4A | input | Data input of gate 4; overvoltage tolerant to 5.5 V (VI 0 to 5.5 V) with Schmitt-trigger action. |
| 13 | 4B | input | Data input of gate 4; overvoltage tolerant to 5.5 V (VI 0 to 5.5 V) with Schmitt-trigger action. |
| 14 | VCC | power_in | Supply voltage; recommended operating range 1.65 V to 3.6 V (functional down to 1.2 V). |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | DHVQFN-14(2.5x3) |
| Category | Logic |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| HIGH-level input voltage | VIH | 1.08 | V | VCC = 1.2 V | 4 | ||
| HIGH-level input voltage | VIH | 1.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| LOW-level input voltage | VIL | 0.12 | V | VCC = 1.2 V | 4 | ||
| LOW-level input voltage | VIL | 0.7 | V | VCC = 2.3 V to 2.7 V | 4 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 2.7 V to 3.6 V | 4 | ||
| HIGH-level output voltage | VOH | 1.05 | V | IO = -4 mA; VCC = 1.65 V | 4 | ||
| HIGH-level output voltage | VOH | 1.65 | V | IO = -8 mA; VCC = 2.3 V | 4 | ||
| HIGH-level output voltage | VOH | 2.05 | V | IO = -12 mA; VCC = 2.7 V | 4 | ||
| HIGH-level output voltage | VOH | 2.25 | V | IO = -18 mA; VCC = 3.0 V | 4 | ||
| HIGH-level output voltage | VOH | 2 | V | IO = -24 mA; VCC = 3.0 V | 4 | ||
| LOW-level output voltage | VOL | 0.3 | V | IO = 100 μA; VCC = 1.65 V to 3.6 V; VI = VIH or VIL | 4 | ||
| LOW-level output voltage | VOL | 0.65 | V | IO = 4 mA; VCC = 1.65 V | 4 | ||
| LOW-level output voltage | VOL | 0.8 | V | IO = 8 mA; VCC = 2.3 V | 4 | ||
| LOW-level output voltage | VOL | 0.6 | V | IO = 12 mA; VCC = 2.7 V | 4 | ||
| input leakage current | II | -20 | 0.1 | 20 | μA | VCC = 3.6 V; VI = 5.5 V or GND | 4 |
| supply current (static) | ICC | 0.1 | 40 | μA | VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 4 | |
| additional supply current per input pin | ΔICC | 5 | 5000 | μA | per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 4 | |
| propagation delay nA, nB to nY | tpd | 0.5 | 4.1 | 11.4 | ns | VCC = 1.65 V to 1.95 V; nA, nB to nY; see Fig. 4 | 5 |
| propagation delay nA, nB to nY | tpd | 1 | 2.4 | 6.5 | ns | VCC = 2.3 V to 2.7 V; nA, nB to nY; see Fig. 4 | 5 |
| propagation delay nA, nB to nY | tpd | 1 | 2.5 | 7 | ns | VCC = 2.7 V; nA, nB to nY; see Fig. 4 | 5 |
| propagation delay nA, nB to nY | tpd | 1 | 2.2 | 6 | ns | VCC = 3.0 V to 3.6 V; nA, nB to nY; see Fig. 4 | 5 |
| output skew time | tsk(o) | 1.5 | ns | VCC = 3.0 V to 3.6 V; per gate; VI = GND to VCC | 5 | ||
| supply voltage | VCC | 1.65 | 3.6 | V | 3 | ||
| supply voltage for functional operation | 1.2 | V | functional | 3 | |||
| input voltage | VI | 0 | 5.5 | V | 3 | ||
| output voltage | VO | 0 | V | 3 | |||
| ambient temperature in free air | Tamb | -40 | 125 | °C | 3 | ||
| input transition rise and fall rate | Δt/ΔV | 0 | 20 | ns/V | VCC = 1.65 V to 2.7 V | 3 | |
| input transition rise and fall rate | Δt/ΔV | 0 | 10 | ns/V | VCC = 2.7 V to 3.6 V | 3 | |
| supply voltage | VCC | -0.5 | 6.5 | V | 3 | ||
| input clamping current | IIK | -50 | mA | VI < 0 | 3 | ||
| input voltage | VI | -0.5 | 6.5 | V | 3 | ||
| output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 | 3 | |
| output voltage | VO | -0.5 | V | 3 | |||
| output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 3 | |
| supply current | ICC | 100 | mA | 3 | |||
| ground current | IGND | -100 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 |
CAD (KiCad official)
- Symbol:
74LVC86ABQ - Footprint:
Package_DFN_QFN:DHVQFN-14-1EP_2.5x3mm_P0.5mm_EP1x1.5mm - 3D model: DHVQFN-14(2.5x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74lvc86abq-etched.step/74lvc86abq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc86abq.step/74lvc86abq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
aa449c7949d141d5, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).