component
74LVC74APW
Public Made by Adomby adom
Nexperia Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# 74LVC74APW++**Nexperia** · Flip Flops · TSSOP-14++74LVC74APW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1RD | input | Asynchronous reset-direct input (active LOW) for flip-flop 1; resets output independent of clock input. |+| 2 | 1D | input | Data input for flip-flop 1; transfers to Q output on LOW-to-HIGH clock transition; must be stable one setup time prior to clock edge. |+| 3 | 1CP | input | Clock input for flip-flop 1 (LOW-to-HIGH edge-triggered); data transfers to output on rising edge. |+| 4 | 1SD | input | Asynchronous set-direct input (active LOW) for flip-flop 1; sets output independent of clock input. |+| 5 | 1Q | output | True output of flip-flop 1; direct Q output. |+| 6 | 1Q | output | Complement output of flip-flop 1; inverse Q output (Q̅). |+| 7 | GND | power_in | Ground (0 V); reference potential for all voltage measurements. |+| 8 | 2Q | output | Complement output of flip-flop 2; inverse Q output (Q̅). |+| 9 | 2Q | output | True output of flip-flop 2; direct Q output. |+| 10 | 2SD | input | Asynchronous set-direct input (active LOW) for flip-flop 2; sets output independent of clock input. |+| 11 | 2CP | input | Clock input for flip-flop 2 (LOW-to-HIGH edge-triggered); data transfers to output on rising edge. |+| 12 | 2D | input | Data input for flip-flop 2; transfers to Q output on LOW-to-HIGH clock transition; must be stable one setup time prior to clock edge. |+| 13 | 2RD | input | Asynchronous reset-direct input (active LOW) for flip-flop 2; resets output independent of clock input. |+| 14 | VCC | power_in | Supply voltage; recommended range 1.2 V to 3.6 V; 5 V tolerant inputs. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `74LVC74APW`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `74lvc74apw-etched.step` / `74lvc74apw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc74apw.step` / `74lvc74apw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586202370435268608) (16 pp, sha256 `66c1f80f9550c368`, retrieved 2026-09-18, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74lvc74apw-datasheet.pdf)
page.jsonadded+179@@ -0,0 +1,179 @@+{+ "slug": "74lvc74apw",+ "version": "0.1.0",+ "type": "component",+ "description": "Nexperia Flip Flops, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "74lvc74apw",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "74lvc74apw.kicad_sym",+ "74lvc74apw.kicad_mod",+ "74lvc74apw.glb",+ "74lvc74apw.step",+ "74lvc74apw.lbr",+ "docs/hero.png",+ "docs/74lvc74apw-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "74LVC74APW",+ "manufacturer": "Nexperia",+ "package": "TSSOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586202370435268608",+ "parts": {+ "symbol": "74lvc74apw.kicad_sym",+ "footprint": "74lvc74apw.kicad_mod",+ "model_3d": "74lvc74apw-etched.glb",+ "model_3d_plain": "74lvc74apw.glb",+ "model_3d_step": "74lvc74apw-etched.step",+ "model_3d_step_plain": "74lvc74apw.step",+ "lbr": "74lvc74apw.lbr"+ },+ "distributor_links": {+ "lcsc": "C6100"+ },+ "pins": [+ {+ "number": "1",+ "name": "1RD",+ "type": "input",+ "description": "Asynchronous reset-direct input (active LOW) for flip-flop 1; resets output independent of clock input."+ },+ {+ "number": "2",+ "name": "1D",+ "type": "input",+ "description": "Data input for flip-flop 1; transfers to Q output on LOW-to-HIGH clock transition; must be stable one setup time prior to clock edge."+ },+ {+ "number": "3",+ "name": "1CP",+ "type": "input",+ "description": "Clock input for flip-flop 1 (LOW-to-HIGH edge-triggered); data transfers to output on rising edge."+ },+ {+ "number": "4",+ "name": "1SD",+ "type": "input",+ "description": "Asynchronous set-direct input (active LOW) for flip-flop 1; sets output independent of clock input."+ },+ {+ "number": "5",+ "name": "1Q",+ "type": "output",+ "description": "True output of flip-flop 1; direct Q output."+ },+ {+ "number": "6",+ "name": "1Q",+ "type": "output",+ "description": "Complement output of flip-flop 1; inverse Q output (Q̅)."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground (0 V); reference potential for all voltage measurements."+ },+ {+ "number": "8",+ "name": "2Q",+ "type": "output",+ "description": "Complement output of flip-flop 2; inverse Q output (Q̅)."+ },+ {+ "number": "9",+ "name": "2Q",+ "type": "output",+ "description": "True output of flip-flop 2; direct Q output."+ },+ {+ "number": "10",+ "name": "2SD",+ "type": "input",+ "description": "Asynchronous set-direct input (active LOW) for flip-flop 2; sets output independent of clock input."+ },+ {+ "number": "11",+ "name": "2CP",+ "type": "input",+ "description": "Clock input for flip-flop 2 (LOW-to-HIGH edge-triggered); data transfers to output on rising edge."+ },+ {+ "number": "12",+ "name": "2D",+ "type": "input",+ "description": "Data input for flip-flop 2; transfers to Q output on LOW-to-HIGH clock transition; must be stable one setup time prior to clock edge."+ },+ {+ "number": "13",+ "name": "2RD",+ "type": "input",+ "description": "Asynchronous reset-direct input (active LOW) for flip-flop 2; resets output independent of clock input."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; recommended range 1.2 V to 3.6 V; 5 V tolerant inputs."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Output pin signal names in text transcription show as duplicates: pins 5 and 6 both labeled '1Q', pi"+ ],+ "pages_sent": 16,+ "cost_usd": 0.2649,+ "at": "2026-09-18T02:40:37"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586202370435268608",+ "pages": 16,+ "sha256": "66c1f80f9550c368",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}