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74LVC595APW

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Nexperia Shifting Register, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74LVC595APW

Nexperia · Shifting Register · TSSOP-16

74LVC595APW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Parallel data output bit 1 from the 8-bit storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH. Drive capability up to ±24 mA at VCC = 3.0 V.
2 Q2 output Parallel data output bit 2 from the 8-bit storage register. 3-state output controlled by OE.
3 Q3 output Parallel data output bit 3 from the 8-bit storage register. 3-state output controlled by OE.
4 Q4 output Parallel data output bit 4 from the 8-bit storage register. 3-state output controlled by OE.
5 Q5 output Parallel data output bit 5 from the 8-bit storage register. 3-state output controlled by OE.
6 Q6 output Parallel data output bit 6 from the 8-bit storage register. 3-state output controlled by OE.
7 Q7 output Parallel data output bit 7 (MSB) from the 8-bit storage register. 3-state output controlled by OE.
8 GND power_in Ground reference (0 V). Return for all supply and signal currents.
9 Q7S output Serial data output taken from the last (8th) stage of the shift register. Used to cascade multiple 74LVC595A devices; connect to DS of the next stage. Not 3-stated by OE.
10 MR input Master reset, active LOW. A LOW on MR asynchronously clears the shift register only; the storage register contents (Qn) are unaffected until STCP is toggled. Schmitt-trigger input.
11 SHCP input Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP. Schmitt-trigger input; fmax up to 130 MHz min at VCC = 3.0-3.6 V.
12 STCP input Storage register clock input (latch). LOW-to-HIGH transition transfers the contents of the shift register to the 8-bit storage register that drives Q0-Q7. Schmitt-trigger input.
13 OE input Output enable, active LOW. LOW enables the Q0-Q7 parallel outputs; HIGH places them in high-impedance (3-state) OFF-state. Does not affect the state of the internal registers or Q7S. Schmitt-trigger input.
14 DS input Serial data input. Data present on DS is loaded into shift-register stage 0 on the LOW-to-HIGH transition of SHCP. Schmitt-trigger input; setup time ~2 ns typical at VCC = 3.0-3.6 V.
15 Q0 output Parallel data output bit 0 (LSB) from the 8-bit storage register. 3-state output controlled by OE.
16 VCC power_in Supply voltage. Operating range 1.65 V to 3.6 V (functional down to 1.2 V); overvoltage-tolerant inputs to 5.5 V allow use as a 3.3 V ↔ 5 V level translator. Absolute maximum 6.5 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74LVC595APW
  • 74LVC595APWD
  • 74LVC595APWBQ

CAD (KiCad official)

  • Symbol: 74LVC595APW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74lvc595apw-etched.step / 74lvc595apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc595apw.step / 74lvc595apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 d958e095faad6606, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF