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74LVC595ABQ

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Nexperia Shift Registers, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC595ABQ

Nexperia · Shift Registers · DHVQFN-16-EP(2.5x3.5)

74LVC595ABQ from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel 3-state data output Q1 from the storage register; it goes to high impedance when OE is HIGH.
2 Q2 tri_state Parallel 3-state data output Q2 from the storage register; it goes to high impedance when OE is HIGH.
3 Q3 tri_state Parallel 3-state data output Q3 from the storage register; it goes to high impedance when OE is HIGH.
4 Q4 tri_state Parallel 3-state data output Q4 from the storage register; it goes to high impedance when OE is HIGH.
5 Q5 tri_state Parallel 3-state data output Q5 from the storage register; it goes to high impedance when OE is HIGH.
6 Q6 tri_state Parallel 3-state data output Q6 from the storage register; it goes to high impedance when OE is HIGH.
7 Q7 tri_state Parallel 3-state data output Q7 from the storage register; it goes to high impedance when OE is HIGH.
8 GND power_in Ground (0 V) reference for the device.
9 Q7S output Serial data output Q7S used to cascade devices by feeding the next device's DS input.
10 MR input Master reset, active LOW; a LOW resets only the shift register, not the storage register.
11 SHCP input Shift register clock input; data is shifted into the shift register on LOW-to-HIGH transitions.
12 STCP input Storage register clock input; shift register contents are transferred to the storage register on a LOW-to-HIGH transition.
13 OE input Output enable input, active LOW; a HIGH forces the parallel outputs Qn into the high-impedance OFF-state without changing the register contents.
14 DS input Serial data input to shift register stage 0.
15 Q0 tri_state Parallel 3-state data output Q0 from the storage register; it goes to high impedance when OE is HIGH.
16 VCC power_in Supply voltage; recommended operating range 1.65 V to 3.6 V (functional down to 1.2 V), absolute maximum 6.5 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-16-EP(2.5x3.5)
Category Logic
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC 1.65 3.6 V 6
VCC functional supply voltage VCC 1.2 V functional 6
Input voltage VI 0 5.5 V 6
Output voltage 3-state VO 0 5.5 V 3-state 6
Output voltage HIGH or LOW state VO 0 V output HIGH or LOW state; printed max is VCC 6
Ambient temperature Tamb -40 125 °C 6
Input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 6
Input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 6
Supply voltage VCC -0.5 6.5 V 5
Input clamping current IIK -50 mA VI < 0 V 5
Input voltage VI -0.5 6.5 V see note [1] 5
Output voltage 3-state VO -0.5 6.5 V 3-state; see note [1] 5
Output voltage HIGH or LOW state VO -0.5 V output HIGH or LOW state; printed max is VCC + 0.5 V 5
Output current IO -50 50 mA VO = 0 V to VCC 5
Output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 5
Supply current ICC 100 mA 5
Ground current IGND -100 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C; derates 11.2 mW/K above 106 °C (DHVQFN16) 5
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 6
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 6
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 6
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 6
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 6
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 6
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 6
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 6
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 6
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 6
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 6
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 6
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 6
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 6
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 6
Input leakage current II -20 0.1 20 μA VCC = 3.6 V; VI = 5.5 V or GND; typ printed ±0.1 6
OFF-state output current IOZ -20 0.1 20 μA VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V; typ printed ±0.1 7
Power-off leakage current IOFF 0.1 20 μA VCC = 0 V; VI or VO = 5.5 V 7
Supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 7
Additional supply current per input pin ΔICC 5 5000 μA per input pin; VCC = 1.65 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 7
SHCP to Q7S propagation delay tpd 2 6.6 18.2 ns VCC = 1.65 V to 1.95 V; SHCP to Q7S; see Fig. 5 7
SHCP to Q7S propagation delay tpd 1.5 4.2 9.3 ns VCC = 2.3 V to 2.7 V; SHCP to Q7S; see Fig. 5 7
SHCP to Q7S propagation delay tpd 1.5 4.7 8.7 ns VCC = 2.7 V; SHCP to Q7S; see Fig. 5 7
SHCP to Q7S propagation delay tpd 1.5 4 7.7 ns VCC = 3.0 V to 3.6 V; SHCP to Q7S; see Fig. 5 7
STCP to Qn propagation delay tpd 2 5.8 18.2 ns VCC = 1.65 V to 1.95 V; STCP to Qn; see Fig. 6 7
STCP to Qn propagation delay tpd 1.5 3.7 9.3 ns VCC = 2.3 V to 2.7 V; STCP to Qn; see Fig. 6 7
STCP to Qn propagation delay tpd 1.5 4 8.7 ns VCC = 2.7 V; STCP to Qn; see Fig. 6 7
STCP to Qn propagation delay tpd 1.2 3.3 7.7 ns VCC = 3.0 V to 3.6 V; STCP to Qn; see Fig. 6 7
OE to Qn enable time ten 1.2 3.8 7.7 ns VCC = 3.0 V to 3.6 V; OE to Qn; see Fig. 10 8
OE to Qn disable time tdis 1.2 3.5 6.5 ns VCC = 3.0 V to 3.6 V; OE to Qn; see Fig. 10 8
SHCP, STCP pulse width HIGH or LOW tW 7 2.5 ns VCC = 1.65 V to 1.95 V; SHCP, STCP HIGH or LOW; see Fig. 5 and Fig. 6 8
SHCP, STCP pulse width HIGH or LOW tW 4.5 1.5 ns VCC = 3.0 V to 3.6 V; SHCP, STCP HIGH or LOW; see Fig. 5 and Fig. 6 8
Maximum frequency SHCP or STCP fmax 70 130 MHz VCC = 1.65 V to 1.95 V; see Fig. 5 and Fig. 6 9
Maximum frequency SHCP or STCP fmax 90 140 MHz VCC = 2.3 V to 2.7 V; see Fig. 5 and Fig. 6 9
Maximum frequency SHCP or STCP fmax 100 150 MHz VCC = 2.7 V; see Fig. 5 and Fig. 6 9
Maximum frequency SHCP or STCP fmax 115 180 MHz VCC = 3.0 V to 3.6 V; see Fig. 5 and Fig. 6 9
Master reset recovery time trec 2.5 -1 ns VCC = 3.0 V to 3.6 V; MR to SHCP; see Fig. 9 9

CAD (KiCad official)

  • Symbol: 74LVC595ABQ
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74lvc595abq-etched.step / 74lvc595abq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc595abq.step / 74lvc595abq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 d958e095faad6606, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF