component

74LVC573APW

Public Made by Adom

by adom

Nexperia Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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74LVC573APW

Nexperia · Latches · TSSOP-20

74LVC573APW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable input, active LOW. When HIGH, all Q outputs are placed in the high-impedance OFF-state; when LOW, outputs are driven per the latch state. Does not affect stored latch data.
2 D0 input Data input bit 0 to latch 1. Schmitt-trigger CMOS input, 5 V tolerant. Sampled on the HIGH-to-LOW transition of LE.
3 D1 input Data input bit 1 to latch 2. Schmitt-trigger CMOS input, 5 V tolerant.
4 D2 input Data input bit 2 to latch 3. Schmitt-trigger CMOS input, 5 V tolerant.
5 D3 input Data input bit 3 to latch 4. Schmitt-trigger CMOS input, 5 V tolerant.
6 D4 input Data input bit 4 to latch 5. Schmitt-trigger CMOS input, 5 V tolerant.
7 D5 input Data input bit 5 to latch 6. Schmitt-trigger CMOS input, 5 V tolerant.
8 D6 input Data input bit 6 to latch 7. Schmitt-trigger CMOS input, 5 V tolerant.
9 D7 input Data input bit 7 to latch 8. Schmitt-trigger CMOS input, 5 V tolerant.
10 GND power_in Ground reference, 0 V.
11 LE input Latch enable input, active HIGH. When HIGH the latches are transparent (Q follows D); on the HIGH-to-LOW transition the input data is stored. Minimum HIGH pulse width 3.2 ns at VCC = 3.0 V to 3.6 V.
12 Q7 tri_state 3-state data output bit 7. Drives up to -24 mA/+24 mA at VCC = 3.0 V; high-impedance when OE is HIGH.
13 Q6 tri_state 3-state data output bit 6. Drives up to -24 mA/+24 mA at VCC = 3.0 V; high-impedance when OE is HIGH.
14 Q5 tri_state 3-state data output bit 5. Drives up to -24 mA/+24 mA at VCC = 3.0 V; high-impedance when OE is HIGH.
15 Q4 tri_state 3-state data output bit 4. Drives up to -24 mA/+24 mA at VCC = 3.0 V; high-impedance when OE is HIGH.
16 Q3 tri_state 3-state data output bit 3. Drives up to -24 mA/+24 mA at VCC = 3.0 V; high-impedance when OE is HIGH.
17 Q2 tri_state 3-state data output bit 2. Drives up to -24 mA/+24 mA at VCC = 3.0 V; high-impedance when OE is HIGH.
18 Q1 tri_state 3-state data output bit 1. Drives up to -24 mA/+24 mA at VCC = 3.0 V; high-impedance when OE is HIGH.
19 Q0 tri_state 3-state data output bit 0. Drives up to -24 mA/+24 mA at VCC = 3.0 V; high-impedance when OE is HIGH.
20 VCC power_in Supply voltage. Recommended operating range 1.65 V to 3.6 V (functional down to 1.2 V). Absolute maximum 6.5 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

  • 74LVC573APW
  • 74LVC573APWD
  • 74LVC573APWBQ

CAD (KiCad official)

  • Symbol: 74LVC573APW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lvc573apw-etched.step / 74lvc573apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc573apw.step / 74lvc573apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 fc791a4ee5d2cc1f, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF