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74LVC4245APW

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Nexperia Translators, Level Shifters, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC4245APW

Nexperia · Translators, Level Shifters · TSSOP-24

74LVC4245APW from Nexperia, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC(A) power_in Supply voltage for the 5 V bus, 1.5 V to 5.5 V under recommended operating conditions, and must be at or above VCC(B) except in suspend mode.
2 DIR input Direction control: LOW selects B-to-A transfer (Bn inputs, An outputs) and HIGH selects A-to-B transfer (An inputs, Bn outputs), per the functional table.
3 A0 bidirectional Data input or output on the 5 V bus A side, 3-state when OE is HIGH, 5 V tolerant, and high-impedance when VCC(A) = 0 V.
4 A1 bidirectional Data input or output on the 5 V bus A side, 3-state when OE is HIGH, 5 V tolerant, and high-impedance when VCC(A) = 0 V.
5 A2 bidirectional Data input or output on the 5 V bus A side, 3-state when OE is HIGH, 5 V tolerant, and high-impedance when VCC(A) = 0 V.
6 A3 bidirectional Data input or output on the 5 V bus A side, 3-state when OE is HIGH, 5 V tolerant, and high-impedance when VCC(A) = 0 V.
7 A4 bidirectional Data input or output on the 5 V bus A side, 3-state when OE is HIGH, 5 V tolerant, and high-impedance when VCC(A) = 0 V.
8 A5 bidirectional Data input or output on the 5 V bus A side, 3-state when OE is HIGH, 5 V tolerant, and high-impedance when VCC(A) = 0 V.
9 A6 bidirectional Data input or output on the 5 V bus A side, 3-state when OE is HIGH, 5 V tolerant, and high-impedance when VCC(A) = 0 V.
10 A7 bidirectional Data input or output on the 5 V bus A side, 3-state when OE is HIGH, 5 V tolerant, and high-impedance when VCC(A) = 0 V.
11 GND power_in Ground (0 V) reference for the device.
12 GND power_in Ground (0 V) reference for the device.
13 GND power_in Ground (0 V) reference for the device.
14 B7 bidirectional Data input or output on the 3 V bus B side, which goes to the high-impedance OFF-state when OE is HIGH.
15 B6 bidirectional Data input or output on the 3 V bus B side, which goes to the high-impedance OFF-state when OE is HIGH.
16 B5 bidirectional Data input or output on the 3 V bus B side, which goes to the high-impedance OFF-state when OE is HIGH.
17 B4 bidirectional Data input or output on the 3 V bus B side, which goes to the high-impedance OFF-state when OE is HIGH.
18 B3 bidirectional Data input or output on the 3 V bus B side, which goes to the high-impedance OFF-state when OE is HIGH.
19 B2 bidirectional Data input or output on the 3 V bus B side, which goes to the high-impedance OFF-state when OE is HIGH.
20 B1 bidirectional Data input or output on the 3 V bus B side, which goes to the high-impedance OFF-state when OE is HIGH.
21 B0 bidirectional Data input or output on the 3 V bus B side, which goes to the high-impedance OFF-state when OE is HIGH.
22 OE input Active-LOW output enable; a HIGH level puts the A and B outputs into the high-impedance OFF-state, isolating the buses.
23 VCC(B) power_in Supply voltage for the 3 V bus, 1.5 V to 3.6 V under recommended operating conditions, and must not exceed VCC(A) except in suspend mode.
24 VCC(B) power_in Supply voltage for the 3 V bus, 1.5 V to 3.6 V under recommended operating conditions, and must not exceed VCC(A) except in suspend mode.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-24
Category Logic
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage A (VCC(A)), recommended VCC(A) 1.5 5.5 V VCC(A) ≥ VCC(B); see Fig. 3 for maximum speed performance 5
Supply voltage B (VCC(B)), recommended VCC(B) 1.5 3.6 V VCC(A) ≥ VCC(B); see Fig. 3 for low-voltage applications 5
Input voltage for control inputs, recommended VI 0 5.5 V 5
Output voltage, output HIGH or LOW state, recommended (max printed as VCC) VO 0 V output HIGH or LOW state 5
Output voltage, output 3-state, recommended VO 0 5.5 V output 3-state 5
Ambient temperature, recommended Tamb -40 125 °C 5
Input transition rise and fall rate Δt/ΔV 20 ns/V VCC(B) = 2.7 V to 3.0 V 5
Input transition rise and fall rate Δt/ΔV 10 ns/V VCC(B) = 3.0 V to 3.6 V 5
Supply voltage A, absolute maximum VCC(A) -0.5 6.5 V 4
Supply voltage B, absolute maximum VCC(B) -0.5 4.6 V 4
Input voltage, absolute maximum VI -0.5 6.5 V [1] may be exceeded if input and output current ratings are observed 4
Output voltage, output HIGH or LOW state, absolute maximum (max printed as VCC + 0.5) VO -0.5 V output HIGH or LOW state [1] 4
Output voltage, output 3-state, absolute maximum VO -0.5 6.5 V output 3-state [1] 4
Output current, absolute maximum IO -50 50 mA VO = 0 V to VCCO [2] 4
Supply current, absolute maximum ICC 100 mA 4
Total power dissipation, absolute maximum Ptot 500 mW Tamb = -40 °C to +125 °C [3] 4
HIGH-level input voltage VIH 2 V VCC(B) = 2.7 V to 3.6 V 7
LOW-level input voltage VIL 0.8 V VCC(B) = 2.7 V to 3.6 V 7
LOW-level output voltage VOL 0.3 V VCC(B) = 2.7 V to 3.6 V; IO = 100 μA 7
LOW-level output voltage VOL 0.6 V VCC(B) = 2.7 V; IO = 12 mA 7
LOW-level output voltage VOL 0.8 V VCC(B) = 3.0 V; IO = 24 mA 7
Input leakage current II -20 20 μA VI = 5.5 V or GND 7
OFF-state output current IOZ -20 20 μA VI = VIH or VIL; VCC(B) = 3.6 V; VO = VCC(B) or GND 7
Supply current ICC 40 μA VCC(B) = 3.6 V; other inputs at VCC(B) or GND; IO = 0 A 7
Additional supply current ΔICC 5000 μA VCC(B) = 2.7 V to 3.6 V; VI = VCC(B) - 0.6 V; other inputs at VCC(B) or GND 7
HIGH to LOW propagation delay tPHL tPHL 1 3.6 8 ns An to Bn; see Fig. 4; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
HIGH to LOW propagation delay tPHL tPHL 1 3.3 8 ns An to Bn; see Fig. 4; VCC(B) = 3.0 V to 3.6 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
HIGH to LOW propagation delay tPHL tPHL 1 3.4 8 ns Bn to An; see Fig. 4; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
LOW to HIGH propagation delay tPLH tPLH 1 3.3 8.5 ns An to Bn; see Fig. 4; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
LOW to HIGH propagation delay tPLH tPLH 1 2.8 8.5 ns An to Bn; see Fig. 4; VCC(B) = 3.0 V to 3.6 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
LOW to HIGH propagation delay tPLH tPLH 1 3 6.5 ns Bn to An; see Fig. 4; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
OFF-state to LOW propagation delay tPZL tPZL 1 4.5 11.5 ns OE to An; see Fig. 5; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
OFF-state to LOW propagation delay tPZL tPZL 1 4.4 11 ns OE to Bn; see Fig. 5; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
OFF-state to LOW propagation delay tPZL tPZL 1 3.8 10.5 ns OE to Bn; see Fig. 5; VCC(B) = 3.0 V to 3.6 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
OFF-state to HIGH propagation delay tPZH tPZH 1 4.5 10.5 ns OE to An; see Fig. 5; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
OFF-state to HIGH propagation delay tPZH tPZH 1 4.3 11 ns OE to Bn; see Fig. 5; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
OFF-state to HIGH propagation delay tPZH tPZH 1 3.2 10.5 ns OE to Bn; see Fig. 5; VCC(B) = 3.0 V to 3.6 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
LOW to OFF-state propagation delay tPLZ tPLZ 1 2.9 9 ns OE to An; see Fig. 5; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
LOW to OFF-state propagation delay tPLZ tPLZ 1 3.9 10 ns OE to Bn; see Fig. 5; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
LOW to OFF-state propagation delay tPLZ tPLZ 1 3.5 10 ns OE to Bn; see Fig. 5; VCC(B) = 3.0 V to 3.6 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
HIGH to OFF-state propagation delay tPHZ tPHZ 1 2.8 7.5 ns OE to An; see Fig. 5; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
HIGH to OFF-state propagation delay tPHZ tPHZ 1 3.3 10 ns OE to Bn; see Fig. 5; VCC(B) = 2.7 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
HIGH to OFF-state propagation delay tPHZ tPHZ 1 2.9 10 ns OE to Bn; see Fig. 5; VCC(B) = 3.0 V to 3.6 V; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8
Output skew time tsk(o) tsk(o) 1.5 ns [2] skew between any two outputs of same package switching in same direction; VCC(A) = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns 8

CAD (KiCad official)

  • Symbol: 74LVC4245APW
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: 74lvc4245apw-etched.step / 74lvc4245apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc4245apw.step / 74lvc4245apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 9aad923a337d0d68, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF