# 74LVC3G04DC

**Nexperia** · Inverters · VSSOP-8-0.5mm

74LVC3G04DC from Nexperia, in a VSSOP-8-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input to inverter 1. CMOS input with Schmitt-trigger action; 5 V tolerant. VIH ≥ 0.65×VCC (VCC=1.65-1.95 V) up to 0.7×VCC (VCC=4.5-5.5 V). |
| 2 | 3Y | output | Data output of inverter 3 (Y = NOT A). CMOS push-pull output; ±24 mA drive at VCC = 3.0 V. Disabled by IOFF circuitry when VCC = 0 V. |
| 3 | 2A | input | Data input to inverter 2. CMOS input with Schmitt-trigger action; 5 V tolerant. VIH ≥ 0.65×VCC (VCC=1.65-1.95 V) up to 0.7×VCC (VCC=4.5-5.5 V). |
| 4 | GND | power_in | Ground reference (0 V). Sinks up to 100 mA. All device voltages are referenced to this pin. |
| 5 | 2Y | output | Data output of inverter 2 (Y = NOT A). CMOS push-pull output; ±24 mA drive at VCC = 3.0 V. Disabled by IOFF circuitry when VCC = 0 V. |
| 6 | 3A | input | Data input to inverter 3. CMOS input with Schmitt-trigger action; 5 V tolerant. VIH ≥ 0.65×VCC (VCC=1.65-1.95 V) up to 0.7×VCC (VCC=4.5-5.5 V). |
| 7 | 1Y | output | Data output of inverter 1 (Y = NOT A). CMOS push-pull output; ±24 mA drive at VCC = 3.0 V. Disabled by IOFF circuitry when VCC = 0 V. |
| 8 | VCC | power_in | Positive supply voltage. Operating range 1.65 V to 5.5 V; absolute max 6.5 V. ICC ≤ 4 μA static. Decouple to GND with a 0.1 μF ceramic capacitor near the pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | VSSOP-8-0.5mm |
| Category | Logic |
| Pins | 8 |

## Ordering variants

Same part, different packaging or reel option.

- `74LVC3G04DCDP`
- `74LVC3G04DC`
- `74LVC3G04DCGT`
- `74LVC3G04DCGN`
- `74LVC3G04DCGS`

## CAD (KiCad official)

- Symbol: `74LVC3G04DC`
- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`
- 3D model: VSSOP-8-0.5mm (KiCad packages3D, STEP)
- 3D model files: `74lvc3g04dc-etched.step` / `74lvc3g04dc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc3g04dc.step` / `74lvc3g04dc.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74LVC3G04DC.pdf) (15 pp, sha256 `513758c5eead975e`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74lvc3g04dc-datasheet.pdf)