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74LVC374AD

Public Made by Adom

by adom

Nexperia Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC374AD

Nexperia · Flip Flops · SOIC-20-300mil

74LVC374AD from Nexperia, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-LOW output enable input; a HIGH level forces the Qn outputs into the high-impedance OFF-state without changing the flip-flop contents.
2 Q0 tri_state 3-state flip-flop output 0, which goes high-impedance when OE is HIGH.
3 D0 input Data input 0, stored on the LOW-to-HIGH CP transition when set-up and hold times are met.
4 D1 input Data input 1, stored on the LOW-to-HIGH CP transition when set-up and hold times are met.
5 Q1 tri_state 3-state flip-flop output 1, which goes high-impedance when OE is HIGH.
6 Q2 tri_state 3-state flip-flop output 2, which goes high-impedance when OE is HIGH.
7 D2 input Data input 2, stored on the LOW-to-HIGH CP transition when set-up and hold times are met.
8 D3 input Data input 3, stored on the LOW-to-HIGH CP transition when set-up and hold times are met.
9 Q3 tri_state 3-state flip-flop output 3, which goes high-impedance when OE is HIGH.
10 GND power_in Ground (0 V) reference for all voltages on the device.
11 CP input Clock input, edge-triggered on the LOW-to-HIGH transition; the flip-flops store Dn on this edge.
12 Q4 tri_state 3-state flip-flop output 4, which goes high-impedance when OE is HIGH.
13 D4 input Data input 4, stored on the LOW-to-HIGH CP transition when set-up and hold times are met.
14 D5 input Data input 5, stored on the LOW-to-HIGH CP transition when set-up and hold times are met.
15 Q5 tri_state 3-state flip-flop output 5, which goes high-impedance when OE is HIGH.
16 Q6 tri_state 3-state flip-flop output 6, which goes high-impedance when OE is HIGH.
17 D6 input Data input 6, stored on the LOW-to-HIGH CP transition when set-up and hold times are met.
18 D7 input Data input 7, stored on the LOW-to-HIGH CP transition when set-up and hold times are met.
19 Q7 tri_state 3-state flip-flop output 7, which goes high-impedance when OE is HIGH.
20 VCC power_in Supply voltage; recommended operating range is 1.65 V to 3.6 V (functional down to 1.2 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-20-300mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC -0.5 6.5 V 5
input voltage VI -0.5 6.5 V 5
output voltage VO -0.5 V output HIGH or LOW state 5
output voltage VO -0.5 6.5 V output 3-state 5
output current IO -50 50 mA VO = 0 V to VCC 5
supply current ICC 100 mA 5
storage temperature Tstg -65 150 °C 5
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
supply voltage VCC 1.65 3.6 V 6
supply voltage (functional) VCC 1.2 V functional 6
input voltage VI 0 5.5 V 6
output voltage VO 0 V output HIGH or LOW state 6
output voltage VO 0 5.5 V output 3-state 6
ambient temperature Tamb -40 125 °C in free air 6
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 6
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 6
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 6
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 6
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 6
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 6
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 6
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 6
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 6
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 6
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 6
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 6
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 6
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 6
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 6
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 6
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 6
input leakage current II -20 0.1 20 μA VCC = 3.6 V; VI = 5.5 V or GND 6
power-off leakage current IOFF -20 0.1 20 μA VCC = 0 V; VI or VO = 5.5 V 7
supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 7
additional supply current ΔICC 5 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 7
propagation delay CP to Qn tpd 2.2 7.4 18.8 ns CP to Qn; see Fig. 5; VCC = 1.65 V to 1.95 V 7
propagation delay CP to Qn tpd 1.5 3.9 9.7 ns CP to Qn; see Fig. 5; VCC = 2.3 V to 2.7 V 7
propagation delay CP to Qn tpd 1.5 3.5 10 ns CP to Qn; see Fig. 5; VCC = 2.7 V 7
propagation delay CP to Qn tpd 1.5 3.3 9 ns CP to Qn; see Fig. 5; VCC = 3.0 V to 3.6 V 7
enable time OE to Qn ten 1.5 6.6 19.3 ns OE to Qn; see Fig. 6; VCC = 1.65 V to 1.95 V 7
enable time OE to Qn ten 1.5 3.7 10.8 ns OE to Qn; see Fig. 6; VCC = 2.3 V to 2.7 V 7
enable time OE to Qn ten 1.5 3.8 11 ns OE to Qn; see Fig. 6; VCC = 2.7 V 7
enable time OE to Qn ten 1.5 3 9.5 ns OE to Qn; see Fig. 6; VCC = 3.0 V to 3.6 V 7
pulse width tW 5 ns CP HIGH or LOW; see Fig. 5; VCC = 1.65 V to 1.95 V 8
pulse width tW 4 ns CP HIGH or LOW; see Fig. 5; VCC = 2.3 V to 2.7 V 8
set-up time tsu 4 ns Dn to CP; see Fig. 7; VCC = 1.65 V to 1.95 V 7
set-up time tsu 3 ns Dn to CP; see Fig. 7; VCC = 2.3 V to 2.7 V 7
set-up time tsu 2 ns Dn to CP; see Fig. 7; VCC = 2.7 V 7
set-up time tsu 2 0 ns Dn to CP; see Fig. 7; VCC = 3.0 V to 3.6 V 7
hold time th 3 ns Dn to CP; see Fig. 7; VCC = 1.65 V to 1.95 V 8
hold time th 2 ns Dn to CP; see Fig. 7; VCC = 2.3 V to 2.7 V 8
hold time th 1.5 ns Dn to CP; see Fig. 7; VCC = 2.7 V 8
hold time th 1.5 0.6 ns Dn to CP; see Fig. 7; VCC = 3.0 V to 3.6 V 8
maximum frequency fmax 64 MHz see Fig. 5; VCC = 1.65 V to 1.95 V 8
maximum frequency fmax 100 MHz see Fig. 5; VCC = 2.3 V to 2.7 V 8
maximum frequency fmax 120 MHz see Fig. 5; VCC = 2.7 V 8

CAD (KiCad official)

  • Symbol: 74LVC374AD
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: 74lvc374ad-etched.step / 74lvc374ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc374ad.step / 74lvc374ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 6665bcb5e5f9efc6, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF