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74LVC32APW-Q100J

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Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC32APW-Q100J

Nexperia · Logic Gates · TSSOP-14

74LVC32APW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of gate 1 (OR with 1B), with input voltage rated from 0 V to 5.5 V.
2 1B input Data input 1B of gate 1 (OR with 1A), with input voltage rated from 0 V to 5.5 V.
3 1Y output Data output 1Y of gate 1; output current is limited to ±50 mA (VO = 0 V to VCC).
4 2A input Data input 2A of gate 2 (OR with 2B), with input voltage rated from 0 V to 5.5 V.
5 2B input Data input 2B of gate 2 (OR with 2A), with input voltage rated from 0 V to 5.5 V.
6 2Y output Data output 2Y of gate 2; output current is limited to ±50 mA (VO = 0 V to VCC).
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 3Y output Data output 3Y of gate 3; output current is limited to ±50 mA (VO = 0 V to VCC).
9 3A input Data input 3A of gate 3 (OR with 3B), with input voltage rated from 0 V to 5.5 V.
10 3B input Data input 3B of gate 3 (OR with 3A), with input voltage rated from 0 V to 5.5 V.
11 4Y output Data output 4Y of gate 4; output current is limited to ±50 mA (VO = 0 V to VCC).
12 4A input Data input 4A of gate 4 (OR with 4B), with input voltage rated from 0 V to 5.5 V.
13 4B input Data input 4B of gate 4 (OR with 4A), with input voltage rated from 0 V to 5.5 V.
14 VCC power_in Supply voltage; recommended operating range is 1.65 V to 3.6 V (functional from 1.2 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 1.65 3.6 V 4
functional supply voltage 1.2 V functional 4
input voltage VI 0 5.5 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 4
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 4
supply voltage VCC -0.5 6.5 V 3
input clamping current IIK -50 mA VI < 0 3
input voltage VI -0.5 6.5 V 3
output clamping current IOK -50 50 mA VO > VCC or VO < 0 3
output voltage VO -0.5 V 3
output current IO -50 50 mA VO = 0 V to VCC 3
supply current ICC 100 mA 3
ground current IGND -100 mA 3
storage temperature Tstg -65 150 °C 3
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
HIGH-level input voltage VIH 1.08 V Tamb -40 °C to +125 °C; VCC = 1.2 V 4
HIGH-level input voltage VIH 1.7 V Tamb -40 °C to +125 °C; VCC = 2.3 V to 2.7 V 4
HIGH-level input voltage VIH 2 V Tamb -40 °C to +125 °C; VCC = 2.7 V to 3.6 V 4
LOW-level input voltage VIL 0.12 V Tamb -40 °C to +125 °C; VCC = 1.2 V 4
LOW-level input voltage VIL 0.7 V Tamb -40 °C to +125 °C; VCC = 2.3 V to 2.7 V 4
LOW-level input voltage VIL 0.8 V Tamb -40 °C to +125 °C; VCC = 2.7 V to 3.6 V 4
HIGH-level output voltage VOH 1.05 V Tamb -40 °C to +125 °C; IO = -4 mA; VCC = 1.65 V 4
HIGH-level output voltage VOH 1.65 V Tamb -40 °C to +125 °C; IO = -8 mA; VCC = 2.3 V 4
HIGH-level output voltage VOH 2.05 V Tamb -40 °C to +125 °C; IO = -12 mA; VCC = 2.7 V 4
HIGH-level output voltage VOH 2.25 V Tamb -40 °C to +125 °C; IO = -18 mA; VCC = 3.0 V 4
HIGH-level output voltage VOH 2 V Tamb -40 °C to +125 °C; IO = -24 mA; VCC = 3.0 V 4
LOW-level output voltage VOL 0.3 V Tamb -40 °C to +125 °C; IO = 100 μA; VCC = 1.65 V to 3.6 V 4
LOW-level output voltage VOL 0.65 V Tamb -40 °C to +125 °C; IO = 4 mA; VCC = 1.65 V 4
LOW-level output voltage VOL 0.8 V Tamb -40 °C to +125 °C; IO = 8 mA; VCC = 2.3 V 4
LOW-level output voltage VOL 0.6 V Tamb -40 °C to +125 °C; IO = 12 mA; VCC = 2.7 V 4
input leakage current II -20 20 μA Tamb -40 °C to +125 °C; VCC = 3.6 V; VI = 5.5 V or GND 5
supply current ICC 40 μA Tamb -40 °C to +125 °C; VCC = 3.6 V; VI = VCC or GND; IO = 0 A 5
additional supply current ΔICC 5000 μA Tamb -40 °C to +125 °C; per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 5
propagation delay tpd 0.5 4.2 10.4 ns Tamb -40 °C to +125 °C; nA, nB to nY; VCC = 1.65 V to 1.95 V 5
propagation delay tpd 1.5 2.4 5.7 ns Tamb -40 °C to +125 °C; nA, nB to nY; VCC = 2.3 V to 2.7 V 5
propagation delay tpd 1.5 2.5 5.5 ns Tamb -40 °C to +125 °C; nA, nB to nY; VCC = 2.7 V 5
propagation delay tpd 1 2.2 5 ns Tamb -40 °C to +125 °C; nA, nB to nY; VCC = 3.0 V to 3.6 V 5
output skew time tsk(o) 1.5 ns Tamb -40 °C to +125 °C; per gate; VCC = 3.0 V to 3.6 V 5

CAD (KiCad official)

  • Symbol: 74LVC32APW-Q100J
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvc32apw-q100j-etched.step / 74lvc32apw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc32apw-q100j.step / 74lvc32apw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 1175d361156aa29d, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF