component
74LVC32APW
Public Made by Adomby adom
Nexperia Logic Gates, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LVC32APW
Nexperia · Logic Gates · TSSOP-14
74LVC32APW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A for gate 1; Schmitt-trigger input, VI range 0 V to 5.5 V (overvoltage tolerant), input leakage ±5 µA max at VCC = 3.6 V. |
| 2 | 1B | input | Data input B for gate 1; Schmitt-trigger input, VI range 0 V to 5.5 V (overvoltage tolerant), input leakage ±5 µA max at VCC = 3.6 V. |
| 3 | 1Y | output | Data output for gate 1; OR function of 1A and 1B, VO range 0 V to VCC, IO max ±50 mA. |
| 4 | 2A | input | Data input A for gate 2; Schmitt-trigger input, VI range 0 V to 5.5 V (overvoltage tolerant), input leakage ±5 µA max at VCC = 3.6 V. |
| 5 | 2B | input | Data input B for gate 2; Schmitt-trigger input, VI range 0 V to 5.5 V (overvoltage tolerant), input leakage ±5 µA max at VCC = 3.6 V. |
| 6 | 2Y | output | Data output for gate 2; OR function of 2A and 2B, VO range 0 V to VCC, IO max ±50 mA. |
| 7 | GND | power_in | Ground supply reference, 0 V; ground current IGND min −100 mA. |
| 8 | 3Y | output | Data output for gate 3; OR function of 3A and 3B, VO range 0 V to VCC, IO max ±50 mA. |
| 9 | 3A | input | Data input A for gate 3; Schmitt-trigger input, VI range 0 V to 5.5 V (overvoltage tolerant), input leakage ±5 µA max at VCC = 3.6 V. |
| 10 | 3B | input | Data input B for gate 3; Schmitt-trigger input, VI range 0 V to 5.5 V (overvoltage tolerant), input leakage ±5 µA max at VCC = 3.6 V. |
| 11 | 4Y | output | Data output for gate 4; OR function of 4A and 4B, VO range 0 V to VCC, IO max ±50 mA. |
| 12 | 4A | input | Data input A for gate 4; Schmitt-trigger input, VI range 0 V to 5.5 V (overvoltage tolerant), input leakage ±5 µA max at VCC = 3.6 V. |
| 13 | 4B | input | Data input B for gate 4; Schmitt-trigger input, VI range 0 V to 5.5 V (overvoltage tolerant), input leakage ±5 µA max at VCC = 3.6 V. |
| 14 | VCC | power_in | Positive supply voltage; recommended operating range 1.65 V to 3.6 V (functional from 1.2 V), ICC max 100 mA, Ptot max 500 mW (derates 7.3 mW/K above 81 °C for TSSOP14). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
74LVC32APW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74lvc32apw-etched.step/74lvc32apw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc32apw.step/74lvc32apw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
74c8046303520072, retrieved 2026-09-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).