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74LVC2G66DP

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Nexperia Analog Switches, Multiplexers, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC2G66DP

Nexperia · Analog Switches, Multiplexers · TSSOP-8

74LVC2G66DP from Nexperia, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y bidirectional Independent input/output terminal of switch 1 (bilateral analog switch), with a switch current capability of 32 mA.
2 1Z bidirectional Independent input/output terminal of switch 1 (bilateral analog switch), with a switch current capability of 32 mA.
3 2E input Enable input for switch 2, active HIGH: the switch is OFF when LOW and ON when HIGH.
4 GND power_in Ground (0 V) reference for all voltages.
5 2Y bidirectional Independent input/output terminal of switch 2 (bilateral analog switch), with a switch current capability of 32 mA.
6 2Z bidirectional Independent input/output terminal of switch 2 (bilateral analog switch), with a switch current capability of 32 mA.
7 1E input Enable input for switch 1, active HIGH: the switch is OFF when LOW and ON when HIGH.
8 VCC power_in Supply voltage; recommended operating range is 1.65 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage (absolute maximum) VCC -0.5 6.5 V 4
input voltage (absolute maximum) VI -0.5 6.5 V 4
input clamping current IIK -50 mA VI < -0.5 V or VI > VCC + 0.5 V 4
switch clamping current ISK -50 50 mA VI < -0.5 V or VI > VCC + 0.5 V 4
switch voltage (absolute maximum) VSW -0.5 V enable and disable mode 4
switch current ISW -50 50 mA VSW > -0.5 V or VSW < VCC + 0.5 V 4
supply current (absolute maximum) ICC 100 mA 4
ground current IGND -100 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 250 mW Tamb = -40 °C to +125 °C 4
supply voltage (recommended) VCC 1.65 5.5 V 4
input voltage (recommended) VI 0 5.5 V 4
switch voltage (recommended) VSW 0 V 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 20 ns/V VCC = 1.65 V to 2.7 V 4
input transition rise and fall rate Δt/ΔV 10 ns/V VCC = 2.7 V to 5.5 V 4
HIGH-level input voltage (VCC = 2.3 V to 2.7 V) VIH 1.7 V VCC = 2.3 V to 2.7 V 5
HIGH-level input voltage (VCC = 2.7 V to 3.6 V) VIH 2 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage (VCC = 2.3 V to 2.7 V) VIL 0.7 V VCC = 2.3 V to 2.7 V 5
LOW-level input voltage (VCC = 2.7 V to 3.6 V) VIL 0.8 V VCC = 2.7 V to 3.6 V 5
input leakage current II -1 0.1 1 μA pin nE; VI = 5.5 V or GND; VCC = 0 V to 5.5 V 5
OFF-state leakage current IS(OFF) -0.5 0.1 0.5 μA VCC = 5.5 V; see Fig. 6. 5
ON-state leakage current IS(ON) -2 0.1 2 μA VCC = 5.5 V; see Fig. 7. 5
supply current ICC 0.1 4 μA VI = 5.5 V or GND; VSW = GND or VCC; VCC = 1.65 V to 5.5 V 5
additional supply current ΔICC 5 500 μA pin nE; VI = VCC - 0.6 V; VSW = GND or VCC; VCC = 5.5 V 5
ON resistance (peak) RON(peak) 34 195 Ω VI = GND to VCC; see Fig. 8; ISW = 4 mA; VCC = 1.65 V to 1.95 V 6
ON resistance (peak) RON(peak) 12 45 Ω VI = GND to VCC; see Fig. 8; ISW = 8 mA; VCC = 2.3 V to 2.7 V 6
ON resistance (peak) RON(peak) 10.4 38 Ω VI = GND to VCC; see Fig. 8; ISW = 12 mA; VCC = 2.7 V 6
ON resistance (peak) RON(peak) 7.8 30 Ω VI = GND to VCC; see Fig. 8; ISW = 24 mA; VCC = 3 V to 3.6 V 6
ON resistance (peak) RON(peak) 6.2 23 Ω VI = GND to VCC; see Fig. 8; ISW = 32 mA; VCC = 4.5 V to 5.5 V 6
ON resistance (rail), VI = GND RON(rail) 8.2 27 Ω VI = GND; see Fig. 8; ISW = 4 mA; VCC = 1.65 V to 1.95 V 6
ON resistance (rail), VI = GND RON(rail) 7.1 24 Ω VI = GND; see Fig. 8; ISW = 8 mA; VCC = 2.3 V to 2.7 V 6
ON resistance (rail), VI = GND RON(rail) 6.9 21 Ω VI = GND; see Fig. 8; ISW = 12 mA; VCC = 2.7 V 6
ON resistance (rail), VI = GND RON(rail) 6.5 18 Ω VI = GND; see Fig. 8; ISW = 24 mA; VCC = 3 V to 3.6 V 6
ON resistance (rail), VI = GND RON(rail) 5.8 15 Ω VI = GND; see Fig. 8; ISW = 32 mA; VCC = 4.5 V to 5.5 V 6
ON resistance (rail), VI = VCC RON(rail) 10.4 45 Ω VI = VCC; see Fig. 8; ISW = 4 mA; VCC = 1.65 V to 1.95 V 6
ON resistance (rail), VI = VCC RON(rail) 7.6 30 Ω VI = VCC; see Fig. 8; ISW = 8 mA; VCC = 2.3 V to 2.7 V 6
ON resistance (rail), VI = VCC RON(rail) 7 27 Ω VI = VCC; see Fig. 8; ISW = 12 mA; VCC = 2.7 V 6
ON resistance (rail), VI = VCC RON(rail) 6.1 23 Ω VI = VCC; see Fig. 8; ISW = 24 mA; VCC = 3 V to 3.6 V 6
ON resistance (rail), VI = VCC RON(rail) 4.9 15 Ω VI = VCC; see Fig. 8; ISW = 32 mA; VCC = 4.5 V to 5.5 V 6
propagation delay (nY to nZ or nZ to nY) tpd 0.8 3 ns nY to nZ or nZ to nY; see Fig. 15; VCC = 1.65 V to 1.95 V 9
propagation delay (nY to nZ or nZ to nY) tpd 0.4 2 ns nY to nZ or nZ to nY; see Fig. 15; VCC = 2.3 V to 2.7 V 9
propagation delay (nY to nZ or nZ to nY) tpd 0.4 1.5 ns nY to nZ or nZ to nY; see Fig. 15; VCC = 2.7 V 9
propagation delay (nY to nZ or nZ to nY) tpd 0.3 1.5 ns nY to nZ or nZ to nY; see Fig. 15; VCC = 3.0 V to 3.6 V 9
propagation delay (nY to nZ or nZ to nY) tpd 0.2 1 ns nY to nZ or nZ to nY; see Fig. 15; VCC = 4.5 V to 5.5 V 9
enable time (nE to nY or nZ) ten 1 4.6 13 ns nE to nY or nZ; see Fig. 16; VCC = 1.65 V to 1.95 V 9
enable time (nE to nY or nZ) ten 1 2.7 7.5 ns nE to nY or nZ; see Fig. 16; VCC = 2.3 V to 2.7 V 9
enable time (nE to nY or nZ) ten 1 2.7 6.5 ns nE to nY or nZ; see Fig. 16; VCC = 2.7 V 9
enable time (nE to nY or nZ) ten 1 2.4 6 ns nE to nY or nZ; see Fig. 16; VCC = 3.0 V to 3.6 V 9
enable time (nE to nY or nZ) ten 1 1.8 5 ns nE to nY or nZ; see Fig. 16; VCC = 4.5 V to 5.5 V 9
disable time (nE to nY or nZ) tdis 1 3.8 11.5 ns nE to nY or nZ; see Fig. 16; VCC = 1.65 V to 1.95 V 9
disable time (nE to nY or nZ) tdis 1 2.1 7 ns nE to nY or nZ; see Fig. 16; VCC = 2.3 V to 2.7 V 9
disable time (nE to nY or nZ) tdis 1 3.5 8.5 ns nE to nY or nZ; see Fig. 16; VCC = 2.7 V 9
disable time (nE to nY or nZ) tdis 1 3 8 ns nE to nY or nZ; see Fig. 16; VCC = 3.0 V to 3.6 V 9
disable time (nE to nY or nZ) tdis 1 2.2 6.5 ns nE to nY or nZ; see Fig. 16; VCC = 4.5 V to 5.5 V 9

CAD (KiCad official)

  • Symbol: 74LVC2G66DP
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: 74lvc2g66dp-etched.step / 74lvc2g66dp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc2g66dp.step / 74lvc2g66dp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (22 pp, sha256 847b8b5d8f44f246, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF