component
74LVC2G32DP
Public Made by Adomby adom
Nexperia Logic Gates, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74LVC2G32DP
Nexperia · Logic Gates · TSSOP-8
74LVC2G32DP from Nexperia, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of OR gate 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 2 | 1B | input | Data input 1B of OR gate 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 3 | 2Y | output | Data output 2Y of OR gate 2; outputs are 5 V tolerant in power-down mode (VCC = 0 V) and the IOFF circuitry disables the output when powered down. |
| 4 | GND | power_in | Ground (0 V) reference for all voltages. |
| 5 | 2A | input | Data input 2A of OR gate 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 6 | 2B | input | Data input 2B of OR gate 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 7 | 1Y | output | Data output 1Y of OR gate 1; outputs are 5 V tolerant in power-down mode (VCC = 0 V) and the IOFF circuitry disables the output when powered down. |
| 8 | VCC | power_in | Supply voltage; recommended operating range is 1.65 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-8 |
| Category | Logic |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
74LVC2G32DP - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
74lvc2g32dp-etched.step/74lvc2g32dp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc2g32dp.step/74lvc2g32dp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (19 pp, sha256
60af05d31e096a7d, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74LVC2G32DP
**Nexperia** · Logic Gates · TSSOP-8
74LVC2G32DP from Nexperia, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of OR gate 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 2 | 1B | input | Data input 1B of OR gate 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 3 | 2Y | output | Data output 2Y of OR gate 2; outputs are 5 V tolerant in power-down mode (VCC = 0 V) and the IOFF circuitry disables the output when powered down. |
| 4 | GND | power_in | Ground (0 V) reference for all voltages. |
| 5 | 2A | input | Data input 2A of OR gate 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 6 | 2B | input | Data input 2B of OR gate 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action. |
| 7 | 1Y | output | Data output 1Y of OR gate 1; outputs are 5 V tolerant in power-down mode (VCC = 0 V) and the IOFF circuitry disables the output when powered down. |
| 8 | VCC | power_in | Supply voltage; recommended operating range is 1.65 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-8 |
| Category | Logic |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `74LVC2G32DP`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `74lvc2g32dp-etched.step` / `74lvc2g32dp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74lvc2g32dp.step` / `74lvc2g32dp.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913659725037568) (19 pp, sha256 `60af05d31e096a7d`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74lvc2g32dp-datasheet.pdf)