component

74LVC2G08DP

Public Made by Adom

by adom

Nexperia Logic Gates, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74lvc2g08dpfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 13d ago
viewers 74lvc2g08dp: viewers · Ray 13d ago
74lvc2g08dp-etched.glb 74lvc2g08dp: factory component page (tier=lcsc) · Ray 13d ago
74lvc2g08dp-etched.step 74lvc2g08dp: factory component page (tier=lcsc) · Ray 13d ago
74lvc2g08dp-hero.glb 74lvc2g08dp: hero GLB from the etched model (keeps the MPN mark) · Ray 13d ago
74lvc2g08dp-hero.overlay.json Publish 0.1.0 · Ray 13d ago
74lvc2g08dp.glb Publish 0.1.0 · Ray 13d ago
74lvc2g08dp.kicad_mod Publish 0.1.0 · Ray 13d ago
74lvc2g08dp.kicad_sym Publish 0.1.0 · Ray 13d ago
74lvc2g08dp.lbr Publish 0.1.0 · Ray 13d ago
74lvc2g08dp.step Publish 0.1.0 · Ray 13d ago
package.json Publish 0.1.0 · Ray 13d ago
page.json Set visibility: public · Ray 13d ago
README.md Publish 0.1.0 · Ray 13d ago

74LVC2G08DP

Nexperia · Logic Gates · TSSOP-8

74LVC2G08DP from Nexperia, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input of gate 1; recommended input voltage range is 0 V to 5.5 V, and the input is overvoltage tolerant to 5.5 V with Schmitt-trigger action.
2 1B input Data input of gate 1; recommended input voltage range is 0 V to 5.5 V, and the input is overvoltage tolerant to 5.5 V with Schmitt-trigger action.
3 2Y output Data output of gate 2; in active mode the output voltage is limited to 0 V to VCC, and the outputs are 5 V tolerant.
4 GND power_in Ground (0 V) reference for all voltages on the device.
5 2A input Data input of gate 2; recommended input voltage range is 0 V to 5.5 V, and the input is overvoltage tolerant to 5.5 V with Schmitt-trigger action.
6 2B input Data input of gate 2; recommended input voltage range is 0 V to 5.5 V, and the input is overvoltage tolerant to 5.5 V with Schmitt-trigger action.
7 1Y output Data output of gate 1; in active mode the output voltage is limited to 0 V to VCC, and the outputs are 5 V tolerant.
8 VCC power_in Supply voltage; recommended range is 1.65 V to 5.5 V, with an absolute maximum of 6.5 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-8
Category Logic
Pins 8

CAD (KiCad official)

  • Symbol: 74LVC2G08DP
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: 74lvc2g08dp-etched.step / 74lvc2g08dp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc2g08dp.step / 74lvc2g08dp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (20 pp, sha256 f44a89dd7d237b30, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF