74LVC2G02DC-Q100H

{
  "slug": "74lvc2g02dc-q100h",
  "version": "0.1.0",
  "type": "component",
  "description": "Nexperia Logic Gates, VSSOP-8-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "logic",
    "74lvc2g02dc-q100h",
    "factory-2.0.0",
    "extractor-text"
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    "74lvc2g02dc-q100h.glb",
    "74lvc2g02dc-q100h.step",
    "74lvc2g02dc-q100h.lbr",
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    "docs/74lvc2g02dc-q100h-datasheet.pdf",
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    "viewers/footprint.html",
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    "74lvc2g02dc-q100h-hero.overlay.json",
    "74lvc2g02dc-q100h-etched.glb"
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  "component": {
    "mpn": "74LVC2G02DC-Q100H",
    "manufacturer": "Nexperia",
    "package": "VSSOP-8-0.5mm",
    "pin_count": 8,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914717289566208",
    "parts": {
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      "footprint": "74lvc2g02dc-q100h.kicad_mod",
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      "model_3d_step": "74lvc2g02dc-q100h-etched.step",
      "model_3d_step_plain": "74lvc2g02dc-q100h.step",
      "lbr": "74lvc2g02dc-q100h.lbr"
    },
    "distributor_links": {
      "lcsc": "C548536",
      "digikey": "1727-74LVC2G02DC-Q100HTR-ND"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T14:41:48Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "1727-74LVC2G02DC-Q100HTR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Data input 1A of NOR gate 1; Schmitt-trigger input, overvoltage tolerant to 5.5 V, and the input voltage range is 0 V to 5.5 V."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Data input 1B of NOR gate 1; Schmitt-trigger input, overvoltage tolerant to 5.5 V, and the input voltage range is 0 V to 5.5 V."
      },
      {
        "number": "3",
        "name": "2Y",
        "type": "output",
        "description": "Data output 2Y of NOR gate 2; 5 V tolerant output, and in active mode the output voltage is limited to 0 V to VCC."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground (0 V) reference for all voltages in the device."
      },
      {
        "number": "5",
        "name": "2A",
        "type": "input",
        "description": "Data input 2A of NOR gate 2; Schmitt-trigger input, overvoltage tolerant to 5.5 V, and the input voltage range is 0 V to 5.5 V."
      },
      {
        "number": "6",
        "name": "2B",
        "type": "input",
        "description": "Data input 2B of NOR gate 2; Schmitt-trigger input, overvoltage tolerant to 5.5 V, and the input voltage range is 0 V to 5.5 V."
      },
      {
        "number": "7",
        "name": "1Y",
        "type": "output",
        "description": "Data output 1Y of NOR gate 1; 5 V tolerant output, and in active mode the output voltage is limited to 0 V to VCC."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage; recommended operating range is 1.65 V to 5.5 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
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        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers and functions are taken from Table 3 (Pin description) on page 2, which is the authorita; The datasheet covers the 74LVC2G02DC-Q100 (SOT765-1 VSSOP8). The requested MPN carries an extra 'H' ; Pin descriptions for inputs and outputs are not given beyond 'data input' and 'data output' in the d"
        ],
        "pages_sent": 12,
        "cost_usd": 0.0633,
        "at": "2026-10-17T14:39:39"
      },
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        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914717289566208",
        "pages": 12,
        "sha256": "e223406c579875fe",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",
        "checked": "2026-10-17",
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      },
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        "file": "74lvc2g02dc-q100h-etched.step",
        "role": "eda",
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        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
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        "zmin_mm": -0.0,
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        "sha256": "06d1f29edb471f923c59f53a57a8700e295e29f66efaac9ca753ce0ab9406830",
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}