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74LVC273PW

Public Made by Adom

by adom

Nexperia Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC273PW

Nexperia · Flip Flops · TSSOP-20

74LVC273PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Master reset input (active LOW); a LOW forces all outputs Qn LOW independently of the clock and data inputs.
2 Q0 output Flip-flop output 0, which takes the state of D0 on the LOW-to-HIGH CP transition and is forced LOW by MR.
3 D0 input Data input 0, a Schmitt-trigger input that is overvoltage tolerant up to 5.5 V.
4 D1 input Data input 1, a Schmitt-trigger input that is overvoltage tolerant up to 5.5 V.
5 Q1 output Flip-flop output 1, which takes the state of D1 on the LOW-to-HIGH CP transition and is forced LOW by MR.
6 Q2 output Flip-flop output 2, which takes the state of D2 on the LOW-to-HIGH CP transition and is forced LOW by MR.
7 D2 input Data input 2, a Schmitt-trigger input that is overvoltage tolerant up to 5.5 V.
8 D3 input Data input 3, a Schmitt-trigger input that is overvoltage tolerant up to 5.5 V.
9 Q3 output Flip-flop output 3, which takes the state of D3 on the LOW-to-HIGH CP transition and is forced LOW by MR.
10 GND power_in Ground (0 V) reference for all voltages on the device.
11 CP input Clock input, edge-triggered on the LOW-to-HIGH transition.
12 Q4 output Flip-flop output 4, which takes the state of D4 on the LOW-to-HIGH CP transition and is forced LOW by MR.
13 D4 input Data input 4, a Schmitt-trigger input that is overvoltage tolerant up to 5.5 V.
14 D5 input Data input 5, a Schmitt-trigger input that is overvoltage tolerant up to 5.5 V.
15 Q5 output Flip-flop output 5, which takes the state of D5 on the LOW-to-HIGH CP transition and is forced LOW by MR.
16 Q6 output Flip-flop output 6, which takes the state of D6 on the LOW-to-HIGH CP transition and is forced LOW by MR.
17 D6 input Data input 6, a Schmitt-trigger input that is overvoltage tolerant up to 5.5 V.
18 D7 input Data input 7, a Schmitt-trigger input that is overvoltage tolerant up to 5.5 V.
19 Q7 output Flip-flop output 7, which takes the state of D7 on the LOW-to-HIGH CP transition and is forced LOW by MR.
20 VCC power_in Supply voltage, recommended range 1.65 V to 3.6 V and functional down to 1.2 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 6.5 V 4
input clamping current IIK -50 mA VI < 0 V 4
input voltage VI -0.5 6.5 V 4
output clamping current IOK 50 mA VO > VCC or VO < 0 V 4
output voltage VO -0.5 V 4
output current IO -50 50 mA VO = 0 V to VCC 4
supply current ICC 100 mA 4
ground current IGND -100 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage VCC 1.65 3.6 V 4
supply voltage functional VCC 1.2 V functional 4
input voltage VI 0 5.5 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 125 °C in free air 4
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 4
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 4
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.12 V VCC = 1.2 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V; -40 °C to +125 °C 5
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V; -40 °C to +125 °C 5
input leakage current II -20 20 μA VCC = 3.6 V; VI = 5.5 V or GND; -40 °C to +125 °C 5
supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A; -40 °C to +125 °C 5
additional supply current ΔICC 5 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A; -40 °C to +125 °C 5
propagation delay CP to Qn tpd 2.5 9.7 22.2 ns CP to Qn; see Fig. 3; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 6
propagation delay CP to Qn tpd 1.8 4.9 11.4 ns CP to Qn; see Fig. 3; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 6
propagation delay CP to Qn tpd 1.5 4.5 10.5 ns CP to Qn; see Fig. 3; VCC = 2.7 V; -40 °C to +125 °C 6
propagation delay CP to Qn tpd 1.5 4.1 10.5 ns CP to Qn; see Fig. 3; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn tPHL 2.4 10.2 23.5 ns MR to Qn; see Fig. 4; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn tPHL 1.7 5.2 12.1 ns MR to Qn; see Fig. 4; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn tPHL 1.5 4.7 11.5 ns MR to Qn; see Fig. 4; VCC = 2.7 V; -40 °C to +125 °C 6
HIGH to LOW propagation delay MR to Qn tPHL 1.5 4.3 11 ns MR to Qn; see Fig. 4; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 6
maximum frequency fmax 64 MHz see Fig. 3; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 7
maximum frequency fmax 80 MHz see Fig. 3; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 7
maximum frequency fmax 150 MHz see Fig. 3; VCC = 2.7 V; -40 °C to +125 °C 7
maximum frequency fmax 150 230 MHz see Fig. 3; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 7
set-up time tsu 5 ns Dn to CP; see Fig. 5; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 6
set-up time tsu 3.5 ns Dn to CP; see Fig. 5; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 6
set-up time tsu 3 1 ns Dn to CP; see Fig. 5; VCC = 2.7 V; -40 °C to +125 °C 6
set-up time tsu 1 0 ns Dn to CP; see Fig. 5; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 6
hold time th 3 ns Dn to CP; see Fig. 5; VCC = 1.65 V to 1.95 V; -40 °C to +125 °C 6
hold time th 2.5 ns Dn to CP; see Fig. 5; VCC = 2.3 V to 2.7 V; -40 °C to +125 °C 6
hold time th 2 -0.2 ns Dn to CP; see Fig. 5; VCC = 2.7 V; -40 °C to +125 °C 6
hold time th 1 0 ns Dn to CP; see Fig. 5; VCC = 3.0 V to 3.6 V; -40 °C to +125 °C 6
output skew time tsk(o) 1.5 ns VCC = 3.0 V to 3.6 V; per flip-flop; VI = GND to VCC; -40 °C to +125 °C 7

CAD (KiCad official)

  • Symbol: 74LVC273PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lvc273pw-etched.step / 74lvc273pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc273pw.step / 74lvc273pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 e3661a6bdd393c1a, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF