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74LVC257AD

Public Made by Adom

by adom

Nexperia Signal Switches / Encoders & Decoders / Multiplexers, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs 74lvc257ad: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
74lvc257ad-etched.fit.json 74lvc257ad: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
74lvc257ad-etched.glb 74lvc257ad: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
74lvc257ad-etched.step 74lvc257ad: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
74lvc257ad-hero.glb 74lvc257ad: hero from the plain model · Ray
74lvc257ad-hero.overlay.json 74lvc257ad: hero from the plain model · Ray
74lvc257ad.glb Publish 0.1.0 · Ray
74lvc257ad.kicad_mod Publish 0.1.0 · Ray
74lvc257ad.kicad_sym Publish 0.1.0 · Ray
74lvc257ad.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
74lvc257ad.step Publish 0.1.0 · Ray
package.json Publish 0.2.1 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json Publish 0.2.1 · Ray
README.md 74lvc257ad: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

74LVC257AD

Nexperia · Signal Switches / Encoders & Decoders / Multiplexers · SOIC-16

74LVC257AD from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S input Common data select input. LOW selects the nI0 inputs, HIGH selects the nI1 inputs, routed to the respective nY outputs. Schmitt-trigger CMOS input, 5.5 V tolerant.
2 1I0 input Channel 1 data input from source 0. Routed to output 1Y when S is LOW and /OE is LOW. Schmitt-trigger CMOS input, 5.5 V tolerant.
3 1I1 input Channel 1 data input from source 1. Routed to output 1Y when S is HIGH and /OE is LOW. Schmitt-trigger CMOS input, 5.5 V tolerant.
4 1Y tri_state Channel 1 3-state multiplexer output. Drives either 1I0 or 1I1 according to S; high-impedance when /OE is HIGH. Rated for 50 Ω transmission-line drive at 85 °C.
5 2I0 input Channel 2 data input from source 0. Routed to output 2Y when S is LOW and /OE is LOW. Schmitt-trigger CMOS input, 5.5 V tolerant.
6 2I1 input Channel 2 data input from source 1. Routed to output 2Y when S is HIGH and /OE is LOW. Schmitt-trigger CMOS input, 5.5 V tolerant.
7 2Y tri_state Channel 2 3-state multiplexer output. Drives either 2I0 or 2I1 according to S; high-impedance when /OE is HIGH. Rated for 50 Ω transmission-line drive at 85 °C.
8 GND power_in Ground reference (0 V). Connect to system ground.
9 3Y tri_state Channel 3 3-state multiplexer output. Drives either 3I0 or 3I1 according to S; high-impedance when /OE is HIGH. Rated for 50 Ω transmission-line drive at 85 °C.
10 3I1 input Channel 3 data input from source 1. Routed to output 3Y when S is HIGH and /OE is LOW. Schmitt-trigger CMOS input, 5.5 V tolerant.
11 3I0 input Channel 3 data input from source 0. Routed to output 3Y when S is LOW and /OE is LOW. Schmitt-trigger CMOS input, 5.5 V tolerant.
12 4Y tri_state Channel 4 3-state multiplexer output. Drives either 4I0 or 4I1 according to S; high-impedance when /OE is HIGH. Rated for 50 Ω transmission-line drive at 85 °C.
13 4I1 input Channel 4 data input from source 1. Routed to output 4Y when S is HIGH and /OE is LOW. Schmitt-trigger CMOS input, 5.5 V tolerant.
14 4I0 input Channel 4 data input from source 0. Routed to output 4Y when S is LOW and /OE is LOW. Schmitt-trigger CMOS input, 5.5 V tolerant.
15 /OE input 3-state output enable input, active LOW. When HIGH, all nY outputs are placed into the high-impedance state; when LOW, outputs follow the selected inputs. Schmitt-trigger CMOS input, 5.5 V tolerant.
16 VCC power_in Positive supply voltage. Recommended operating range 1.65 V to 3.6 V (functional down to 1.2 V); absolute maximum 6.5 V. Decouple locally to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Ordering variants

  • 74LVC257ADD
  • 74LVC257ADPW
  • 74LVC257ADBQ

CAD (KiCad official)

  • Symbol: 74LVC257AD
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74lvc257ad-etched.step / 74lvc257ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc257ad.step / 74lvc257ad.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
74lvc257ad.step 217 KB You want the bare part, or you mark your own boards.
74lvc257ad-etched.step 2.0 MB You want the part with 74LVC257AD already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 522 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 3a23e9adf4d0e855, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF