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74LVC257ABQ

Public Made by Adom

by adom

Nexperia Signal Switches, Multiplexers, Decoders, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC257ABQ

Nexperia · Signal Switches, Multiplexers, Decoders · DHVQFN-16-EP(2.5x3.5)

74LVC257ABQ from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S input Common data select input: S LOW routes nI0 to nY and S HIGH routes nI1 to nY, with input levels specified up to 5.5 V.
2 1I0 input Data input from source 0 for multiplexer 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
3 1I1 input Data input from source 1 for multiplexer 1; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
4 1Y tri_state 3-state multiplexer output 1; high-impedance when OE is HIGH, and output voltage is specified from 0 V to VCC in HIGH or LOW state.
5 2I0 input Data input from source 0 for multiplexer 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
6 2I1 input Data input from source 1 for multiplexer 2; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
7 2Y tri_state 3-state multiplexer output 2; high-impedance when OE is HIGH, and output voltage is specified from 0 V to VCC in HIGH or LOW state.
8 GND power_in Ground (0 V) reference for all voltages.
9 3Y tri_state 3-state multiplexer output 3; high-impedance when OE is HIGH, and output voltage is specified from 0 V to VCC in HIGH or LOW state.
10 3I1 input Data input from source 1 for multiplexer 3; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
11 3I0 input Data input from source 0 for multiplexer 3; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
12 4Y tri_state 3-state multiplexer output 4; high-impedance when OE is HIGH, and output voltage is specified from 0 V to VCC in HIGH or LOW state.
13 4I1 input Data input from source 1 for multiplexer 4; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
14 4I0 input Data input from source 0 for multiplexer 4; inputs are overvoltage tolerant to 5.5 V and have Schmitt-trigger action.
15 OE input 3-state output enable input, active LOW; a HIGH level forces all outputs into the high-impedance OFF-state.
16 VCC power_in Supply voltage: recommended operating range 1.65 V to 3.6 V, functional down to 1.2 V, absolute maximum 6.5 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-16-EP(2.5x3.5)
Category Logic
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 1.65 3.6 V 4
functional supply voltage VCC 1.2 V functional 4
input voltage VI 0 5.5 V 4
output voltage HIGH or LOW state VO 0 V HIGH or LOW state 4
output voltage 3-state VO 0 5.5 V 3-state 4
ambient temperature in free air Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 4
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 4
supply voltage VCC -0.5 6.5 V 4
input clamping current IIK -50 mA VI < 0 4
input voltage VI -0.5 6.5 V 4
output clamping current IOK -50 50 mA VO > VCC or VO < 0 4
output voltage 3-state VO -0.5 6.5 V output 3-state 4
output voltage HIGH or LOW state VO -0.5 V HIGH or LOW state 4
output current IO -50 50 mA VO = 0 V to VCC 4
supply current ICC 100 mA 4
ground current IGND -100 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 5
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 5
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 5
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 5
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 5
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 5
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 5
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 5
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 5
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 5
input leakage current II -20 20 μA VCC = 3.6 V; VI = 5.5 V or GND 5
OFF-state output current IOZ -20 20 μA VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND 5
power-off leakage current IOFF -20 20 μA VCC = 0 V; VI or VO = 5.5 V 5
supply current ICC 0.1 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 5
additional supply current ΔICC 5 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 5
propagation delay nI0, nI1 to nY tpd 1.5 12.3 ns VCC = 1.65 V to 1.95 V; see Fig. 5 6
propagation delay nI0, nI1 to nY tpd 1 6.4 ns VCC = 2.3 V to 2.7 V; see Fig. 5 6
propagation delay nI0, nI1 to nY tpd 1 7 ns VCC = 2.7 V; see Fig. 5 6
propagation delay nI0, nI1 to nY tpd 1 6 ns VCC = 3.0 V to 3.6 V; see Fig. 5 6
propagation delay S to nY tpd 1 17.1 ns VCC = 1.65 V to 1.95 V; see Fig. 5 6
propagation delay S to nY tpd 1 8.9 ns VCC = 2.3 V to 2.7 V; see Fig. 5 6
propagation delay S to nY tpd 1 9.5 ns VCC = 2.7 V; see Fig. 5 6
propagation delay S to nY tpd 1 8 ns VCC = 3.0 V to 3.6 V; see Fig. 5 6
enable time OE to nY ten 1.5 14.7 ns VCC = 1.65 V to 1.95 V; see Fig. 6 6
enable time OE to nY ten 1.5 8.1 ns VCC = 2.3 V to 2.7 V; see Fig. 6 6
enable time OE to nY ten 1.5 8.5 ns VCC = 2.7 V; see Fig. 6 6
enable time OE to nY ten 1 7 ns VCC = 3.0 V to 3.6 V; see Fig. 6 6
disable time OE to nY tdis 2.2 9.4 ns VCC = 1.65 V to 1.95 V; see Fig. 6 6
disable time OE to nY tdis 0.5 5.1 ns VCC = 2.3 V to 2.7 V; see Fig. 6 6
disable time OE to nY tdis 1.5 6 ns VCC = 2.7 V; see Fig. 6 6
disable time OE to nY tdis 1 5.5 ns VCC = 3.0 V to 3.6 V; see Fig. 6 6
output skew time tsk(o) 1.5 ns VCC = 3.0 V to 3.6 V 6

CAD (KiCad official)

  • Symbol: 74LVC257ABQ
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74lvc257abq-etched.step / 74lvc257abq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc257abq.step / 74lvc257abq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 3a23e9adf4d0e855, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF