component

74LVC245APW

Public Made by Adom

by adom

Nexperia Buffer/Driver/Transceiver, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs 74lvc245apw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
74lvc245apw-etched.fit.json 74lvc245apw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
74lvc245apw-etched.glb 74lvc245apw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
74lvc245apw-etched.step 74lvc245apw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
74lvc245apw-hero.glb 74lvc245apw: hero from the plain model · Ray
74lvc245apw-hero.overlay.json 74lvc245apw: hero from the plain model · Ray
74lvc245apw.glb Publish 0.1.0 · Ray
74lvc245apw.kicad_mod Publish 0.1.0 · Ray
74lvc245apw.kicad_sym Publish 0.1.0 · Ray
74lvc245apw.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
74lvc245apw.step Publish 0.1.0 · Ray
package.json Publish 0.2.1 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json Publish 0.2.1 · Ray
README.md 74lvc245apw: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

74LVC245APW

Nexperia · Buffer/Driver/Transceiver · TSSOP-20

74LVC245APW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIR input Direction control input. LOW routes Bn to An (B->A); HIGH routes An to Bn (A->B). CMOS/TTL-compatible Schmitt-trigger input.
2 A0 bidirectional A-side bus data input/output bit 0. Direction set by DIR; enters high-impedance when OE is HIGH.
3 A1 bidirectional A-side bus data input/output bit 1. Direction set by DIR; enters high-impedance when OE is HIGH.
4 A2 bidirectional A-side bus data input/output bit 2. Direction set by DIR; enters high-impedance when OE is HIGH.
5 A3 bidirectional A-side bus data input/output bit 3. Direction set by DIR; enters high-impedance when OE is HIGH.
6 A4 bidirectional A-side bus data input/output bit 4. Direction set by DIR; enters high-impedance when OE is HIGH.
7 A5 bidirectional A-side bus data input/output bit 5. Direction set by DIR; enters high-impedance when OE is HIGH.
8 A6 bidirectional A-side bus data input/output bit 6. Direction set by DIR; enters high-impedance when OE is HIGH.
9 A7 bidirectional A-side bus data input/output bit 7. Direction set by DIR; enters high-impedance when OE is HIGH.
10 GND power_in Ground reference (0 V). Connect to system ground.
11 B7 bidirectional B-side bus data input/output bit 7. Direction set by DIR; enters high-impedance when OE is HIGH.
12 B6 bidirectional B-side bus data input/output bit 6. Direction set by DIR; enters high-impedance when OE is HIGH.
13 B5 bidirectional B-side bus data input/output bit 5. Direction set by DIR; enters high-impedance when OE is HIGH.
14 B4 bidirectional B-side bus data input/output bit 4. Direction set by DIR; enters high-impedance when OE is HIGH.
15 B3 bidirectional B-side bus data input/output bit 3. Direction set by DIR; enters high-impedance when OE is HIGH.
16 B2 bidirectional B-side bus data input/output bit 2. Direction set by DIR; enters high-impedance when OE is HIGH.
17 B1 bidirectional B-side bus data input/output bit 1. Direction set by DIR; enters high-impedance when OE is HIGH.
18 B0 bidirectional B-side bus data input/output bit 0. Direction set by DIR; enters high-impedance when OE is HIGH.
19 OE input Output enable, active LOW. LOW enables the transceiver drivers; HIGH forces both An and Bn buses to the high-impedance OFF-state.
20 VCC power_in Supply voltage input. Recommended operating range 1.65 V to 3.6 V (functional from 1.2 V); absolute maximum 6.5 V. Decouple locally with 100 nF to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

  • 74LVC245APW
  • 74LVC245APWAD
  • 74LVC245APWD
  • 74LVC245APWABQ
  • 74LVC245APWABZ

CAD (KiCad official)

  • Symbol: 74LVC245APW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lvc245apw-etched.step / 74lvc245apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc245apw.step / 74lvc245apw.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
74lvc245apw.step 267 KB You want the bare part, or you mark your own boards.
74lvc245apw-etched.step 2.4 MB You want the part with 74LVC245APW already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 622 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 e87a15c19e7cc6c5, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF