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74LVC245AD

Public Made by Adom

by adom

Nexperia Buffers, Drivers, Receivers, Transceivers, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC245AD

Nexperia · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil

74LVC245AD from Nexperia, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIR input Direction control input that selects the transfer direction between the An and Bn ports as listed in the function selection table (Table 3).
2 A0 bidirectional Data input/output port A0, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
3 A1 bidirectional Data input/output port A1, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
4 A2 bidirectional Data input/output port A2, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
5 A3 bidirectional Data input/output port A3, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
6 A4 bidirectional Data input/output port A4, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
7 A5 bidirectional Data input/output port A5, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
8 A6 bidirectional Data input/output port A6, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
9 A7 bidirectional Data input/output port A7, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
10 GND power_in Ground (0 V) reference for all voltages on the device.
11 B7 bidirectional Data input/output port B7, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
12 B6 bidirectional Data input/output port B6, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
13 B5 bidirectional Data input/output port B5, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
14 B4 bidirectional Data input/output port B4, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
15 B3 bidirectional Data input/output port B3, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
16 B2 bidirectional Data input/output port B2, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
17 B1 bidirectional Data input/output port B1, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
18 B0 bidirectional Data input/output port B0, which goes to the high-impedance OFF-state when OE is HIGH (Table 3).
19 OE input Active-LOW output enable; a HIGH level forces all data outputs into the high-impedance OFF-state (Table 3).
20 VCC power_in Supply voltage; the recommended range is 1.65 V to 3.6 V, with functional operation specified down to 1.2 V (Table 5).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-20-300mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 6.5 V 4
input clamping current IIK -50 mA VI < 0 V 4
input voltage VI -0.5 6.5 V 4
output clamping current IOK -50 50 mA VO > VCC or VO < 0 V 4
output voltage VO -0.5 V output HIGH or LOW 4
output voltage (3-state) VO -0.5 6.5 V output 3-state 4
output current IO -50 50 mA VO = 0 V to VCC 4
supply current ICC 100 mA 4
ground current IGND -100 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C; SOT163-1 (SO20) 4
supply voltage VCC 1.65 3.6 V 5
supply voltage (functional) VCC 1.2 3.6 V functional 5
input voltage VI 0 5.5 V 5
output voltage VO 0 V output HIGH or LOW 5
output voltage (3-state) VO 0 5.5 V output 3-state 5
ambient temperature Tamb -40 125 °C in free air 5
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.2 V to 2.7 V 5
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 5
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 5
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 5
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 5
HIGH-level output voltage VOH 1.05 V VI = VIH or VIL; IO = -4 mA; VCC = 1.65 V 5
HIGH-level output voltage VOH 1.65 V VI = VIH or VIL; IO = -8 mA; VCC = 2.3 V 5
HIGH-level output voltage VOH 2.05 V VI = VIH or VIL; IO = -12 mA; VCC = 2.7 V 5
HIGH-level output voltage VOH 2.25 V VI = VIH or VIL; IO = -18 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 2 V VI = VIH or VIL; IO = -24 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.3 V VI = VIH or VIL; IO = 100 μA; VCC = 1.65 V to 3.6 V 5
LOW-level output voltage VOL 0.65 V VI = VIH or VIL; IO = 4 mA; VCC = 1.65 V 5
LOW-level output voltage VOL 0.8 V VI = VIH or VIL; IO = 8 mA; VCC = 2.3 V 5
LOW-level output voltage VOL 0.6 V VI = VIH or VIL; IO = 12 mA; VCC = 2.7 V 5
input leakage current II -20 20 μA VI = 5.5 V or GND; VCC = 3.6 V 6
OFF-state output current IOZ -20 20 μA VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V 6
power-off leakage current IOFF -20 20 μA VI or VO = 5.5 V; VCC = 0.0 V 6
supply current ICC 0.1 40 μA VI = VCC or GND; IO = 0 A; VCC = 3.6 V 6
additional supply current ΔICC 5 5000 μA per input pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V 6
propagation delay tpd 1.5 6.5 16.9 ns nAn to nBn; nBn to nAn; VCC = 1.65 V to 1.95 V 7
propagation delay tpd 1 3.4 8.7 ns nAn to nBn; nBn to nAn; VCC = 2.3 V to 2.7 V 7
propagation delay tpd 1.5 3.4 9.5 ns nAn to nBn; nBn to nAn; VCC = 2.7 V 7
propagation delay tpd 1.5 2.9 8 ns nAn to nBn; nBn to nAn; VCC = 3.0 V to 3.6 V 7
enable time ten 1.9 8.3 22.5 ns nOE to nAn, nBn; VCC = 1.65 V to 1.95 V 7
enable time ten 1.5 4.6 12.4 ns nOE to nAn, nBn; VCC = 2.3 V to 2.7 V 7
enable time ten 1.5 4.8 12 ns nOE to nAn, nBn; VCC = 2.7 V 7
enable time ten 1.5 3.7 11 ns nOE to nAn, nBn; VCC = 3.0 V to 3.6 V 7
disable time tdis 2.9 5.5 14.2 ns nOE to nAn, nBn; VCC = 1.65 V to 1.95 V 7
disable time tdis 1 3.1 8.2 ns nOE to nAn, nBn; VCC = 2.3 V to 2.7 V 7
disable time tdis 1.5 3.9 10 ns nOE to nAn, nBn; VCC = 2.7 V 7
disable time tdis 1.7 3.6 9 ns nOE to nAn, nBn; VCC = 3.0 V to 3.6 V 7
output skew time tsk(o) 1.5 ns 7

CAD (KiCad official)

  • Symbol: 74LVC245AD
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: 74lvc245ad-etched.step / 74lvc245ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc245ad.step / 74lvc245ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 e87a15c19e7cc6c5, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF