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74LVC240APW

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Nexperia Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74LVC240APW

Nexperia · Logic ICs · TSSOP-20

74LVC240APW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input (active LOW); a HIGH level on 1OE puts outputs 1Y0 to 1Y3 into the high-impedance OFF-state.
2 1A0 input Data input 1A0; the device accepts 3.3 V or 5 V driver levels and its inputs are overvoltage tolerant to 5.5 V.
3 2Y0 tri_state 3-state data output 2Y0 of the 2OE-controlled buffer section; high-impedance when 2OE is HIGH.
4 1A1 input Data input 1A1; the device accepts 3.3 V or 5 V driver levels and its inputs are overvoltage tolerant to 5.5 V.
5 2Y1 tri_state 3-state data output 2Y1 of the 2OE-controlled buffer section; high-impedance when 2OE is HIGH.
6 1A2 input Data input 1A2; the device accepts 3.3 V or 5 V driver levels and its inputs are overvoltage tolerant to 5.5 V.
7 2Y2 tri_state 3-state data output 2Y2 of the 2OE-controlled buffer section; high-impedance when 2OE is HIGH.
8 1A3 input Data input 1A3; the device accepts 3.3 V or 5 V driver levels and its inputs are overvoltage tolerant to 5.5 V.
9 2Y3 tri_state 3-state data output 2Y3 of the 2OE-controlled buffer section; high-impedance when 2OE is HIGH.
10 GND power_in Ground (0 V) reference for all voltages on the device.
11 2A3 input Data input 2A3; the device accepts 3.3 V or 5 V driver levels and its inputs are overvoltage tolerant to 5.5 V.
12 1Y3 tri_state 3-state data output 1Y3 of the 1OE-controlled buffer section; high-impedance when 1OE is HIGH.
13 2A2 input Data input 2A2; the device accepts 3.3 V or 5 V driver levels and its inputs are overvoltage tolerant to 5.5 V.
14 1Y2 tri_state 3-state data output 1Y2 of the 1OE-controlled buffer section; high-impedance when 1OE is HIGH.
15 2A1 input Data input 2A1; the device accepts 3.3 V or 5 V driver levels and its inputs are overvoltage tolerant to 5.5 V.
16 1Y1 tri_state 3-state data output 1Y1 of the 1OE-controlled buffer section; high-impedance when 1OE is HIGH.
17 2A0 input Data input 2A0; the device accepts 3.3 V or 5 V driver levels and its inputs are overvoltage tolerant to 5.5 V.
18 1Y0 tri_state 3-state data output 1Y0 of the 1OE-controlled buffer section; high-impedance when 1OE is HIGH.
19 2OE input Output enable input (active LOW); a HIGH level on 2OE puts outputs 2Y0 to 2Y3 into the high-impedance OFF-state.
20 VCC power_in Power supply; recommended operating range is 1.65 V to 3.6 V (functional down to 1.2 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 6.5 V 4
input clamping current IIK -50 mA VI < 0 4
input voltage VI -0.5 6.5 V 4
output clamping current IOK -50 50 mA VO > VCC or VO < 0 4
output voltage VO -0.5 V output HIGH or LOW state 4
output voltage VO -0.5 6.5 V output 3-state 4
output current IO -50 50 mA VO = 0 V to VCC 4
supply current ICC 100 mA 4
ground current IGND -100 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage VCC 1.65 3.6 V 4
supply voltage (functional) VCC 1.2 V 4
input voltage VI 0 5.5 V 4
output voltage VO 0 V output HIGH or LOW state 4
output voltage VO 0 5.5 V output 3-state 4
ambient temperature Tamb -40 125 °C in free air 4
input transition rise and fall rate Δt/ΔV 0 20 ns/V VCC = 1.65 V to 2.7 V 4
input transition rise and fall rate Δt/ΔV 0 10 ns/V VCC = 2.7 V to 3.6 V 4
HIGH-level input voltage VIH 1.08 V VCC = 1.2 V 5
HIGH-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 5
HIGH-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 5
LOW-level input voltage VIL 0.12 V VCC = 1.2 V 5
LOW-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 5
LOW-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 5
HIGH-level output voltage VOH 1.05 V IO = -4 mA; VCC = 1.65 V 5
HIGH-level output voltage VOH 1.65 V IO = -8 mA; VCC = 2.3 V 5
HIGH-level output voltage VOH 2.05 V IO = -12 mA; VCC = 2.7 V 5
HIGH-level output voltage VOH 2.25 V IO = -18 mA; VCC = 3.0 V 5
HIGH-level output voltage VOH 2 V IO = -24 mA; VCC = 3.0 V 5
LOW-level output voltage VOL 0.3 V IO = 100 μA; VCC = 1.65 V to 3.6 V 5
LOW-level output voltage VOL 0.65 V IO = 4 mA; VCC = 1.65 V 5
LOW-level output voltage VOL 0.8 V IO = 8 mA; VCC = 2.3 V 5
LOW-level output voltage VOL 0.6 V IO = 12 mA; VCC = 2.7 V 5
input leakage current II -20 20 μA VCC = 3.6 V; VI = 5.5 V or GND 5
OFF-state output current IOZ -20 20 μA VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND 5
power-off leakage current IOFF -20 20 μA VCC = 0 V; VI or VO = 5.5 V 5
supply current ICC 40 μA VCC = 3.6 V; VI = VCC or GND; IO = 0 A 5
additional supply current ΔICC 5000 μA per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A 5
propagation delay tpd 1 14.6 ns 1An to 1Yn; 2An to 2Yn; see Fig. 4; VCC = 1.65 V to 1.95 V 6
propagation delay tpd 0.5 7.6 ns 1An to 1Yn; 2An to 2Yn; see Fig. 4; VCC = 2.3 V to 2.7 V 6
propagation delay tpd 1.5 9 ns 1An to 1Yn; 2An to 2Yn; see Fig. 4; VCC = 2.7 V 6
propagation delay tpd 1.3 7 ns 1An to 1Yn; 2An to 2Yn; see Fig. 4; VCC = 3.0 V to 3.6 V 6
enable time ten 1.5 18.3 ns 1OE to 1Yn; 2OE to 2Yn; see Fig. 5; VCC = 1.65 V to 1.95 V 6
enable time ten 1.5 10.1 ns 1OE to 1Yn; 2OE to 2Yn; see Fig. 5; VCC = 2.3 V to 2.7 V 6
enable time ten 1 11 ns 1OE to 1Yn; 2OE to 2Yn; see Fig. 5; VCC = 2.7 V 6
enable time ten 1.1 9 ns 1OE to 1Yn; 2OE to 2Yn; see Fig. 5; VCC = 3.0 V to 3.6 V 6
disable time tdis 2.3 11.4 ns 1OE to 1Yn; 2OE to 2Yn; see Fig. 5; VCC = 1.65 V to 1.95 V 6
disable time tdis 1 6.5 ns 1OE to 1Yn; 2OE to 2Yn; see Fig. 5; VCC = 2.3 V to 2.7 V 6
disable time tdis 1.5 9.5 ns 1OE to 1Yn; 2OE to 2Yn; see Fig. 5; VCC = 2.7 V 6
disable time tdis 1.4 7.5 ns 1OE to 1Yn; 2OE to 2Yn; see Fig. 5; VCC = 3.0 V to 3.6 V 6
output skew time tsk(o) 1.5 ns VCC = 3.0 V to 3.6 V 6

CAD (KiCad official)

  • Symbol: 74LVC240APW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lvc240apw-etched.step / 74lvc240apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc240apw.step / 74lvc240apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 e11da2c032cd1dd0, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF