component
74LVC1T45GM
Public Made by Adomby adom
Nexperia Translators / Level Shifters, XSON-6(1x1.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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| docs | 2d ago |
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| 74lvc1t45gm-etched.step | 2d ago |
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74LVC1T45GM
Nexperia · Translators / Level Shifters · XSON-6(1x1.5)
74LVC1T45GM from Nexperia, in a XSON-6(1x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC(A) | power_in | Supply voltage for port A and DIR, specified from 1.2 V to 5.5 V. |
| 2 | GND | power_in | Ground reference at 0 V; the device enters suspend mode when VCC(A) or VCC(B) is at GND level. |
| 3 | A | bidirectional | Data input or output on the VCC(A)-referenced port, with inputs accepting voltages up to 5.5 V. |
| 4 | B | bidirectional | Data input or output on the VCC(B)-referenced port, with outputs in high-impedance OFF-state in suspend mode. |
| 5 | DIR | input | Direction control referenced to VCC(A): HIGH transmits A to B, LOW transmits B to A. |
| 6 | VCC(B) | power_in | Supply voltage for port B, specified from 1.2 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | XSON-6(1x1.5) |
| Category | Logic ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC(A) supply voltage | VCC(A) | -0.5 | 6.5 | V | 4 | ||
| VCC(B) supply voltage | VCC(B) | -0.5 | 6.5 | V | 4 | ||
| input clamping current | IIK | -50 | mA | VI < 0 V | 4 | ||
| input voltage | VI | -0.5 | 6.5 | V | 4 | ||
| output clamping current | IOK | -50 | mA | VO < 0 V | 4 | ||
| output voltage active mode | VO | -0.5 | V | Active mode; upper limit VCCO + 0.5 V | 4 | ||
| output voltage suspend or 3-state mode | VO | -0.5 | 6.5 | V | Suspend or 3-state mode | 4 | |
| output current | IO | -50 | 50 | mA | VO = 0 V to VCCO | 4 | |
| supply current | ICC | 100 | mA | ICC(A) or ICC(B) | 4 | ||
| ground current | IGND | -100 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 250 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| VCC(A) supply voltage | VCC(A) | 1.2 | 5.5 | V | 5 | ||
| VCC(B) supply voltage | VCC(B) | 1.2 | 5.5 | V | 5 | ||
| input voltage | VI | 0 | 5.5 | V | 5 | ||
| output voltage active mode | VO | 0 | V | Active mode; maximum VCCO | 5 | ||
| output voltage suspend or 3-state mode | VO | 0 | 5.5 | V | Suspend or 3-state mode | 5 | |
| ambient temperature | Tamb | -40 | 125 | °C | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCCI = 1.2 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 10 | ns/V | VCCI = 3 V to 3.6 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 5 | ns/V | VCCI = 4.5 V to 5.5 V | 5 | ||
| HIGH-level input voltage data input | VIH | 1.7 | V | data input; VCCI = 2.3 V to 2.7 V; -40 °C to +125 °C | 6 | ||
| HIGH-level input voltage data input | VIH | 2 | V | data input; VCCI = 3.0 V to 3.6 V; -40 °C to +125 °C | 6 | ||
| LOW-level input voltage data input | VIL | 0.7 | V | data input; VCCI = 2.3 V to 2.7 V; -40 °C to +125 °C | 6 | ||
| LOW-level input voltage data input | VIL | 0.8 | V | data input; VCCI = 3.0 V to 3.6 V; -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 1 | V | VI = VIH; IO = -6 mA; VCCO = 1.4 V | 6 | ||
| HIGH-level output voltage | VOH | 1.2 | V | VI = VIH; IO = -8 mA; VCCO = 1.65 V | 6 | ||
| HIGH-level output voltage | VOH | 1.9 | V | VI = VIH; IO = -12 mA; VCCO = 2.3 V | 6 | ||
| HIGH-level output voltage | VOH | 2.4 | V | VI = VIH; IO = -24 mA; VCCO = 3.0 V | 6 | ||
| HIGH-level output voltage | VOH | 3.8 | V | VI = VIH; IO = -32 mA; VCCO = 4.5 V | 6 | ||
| LOW-level output voltage | VOL | 0.1 | V | VI = VIL; IO = 100 μA; VCCO = 1.2 V to 4.5 V | 6 | ||
| LOW-level output voltage | VOL | 0.3 | V | VI = VIL; IO = 6 mA; VCCO = 1.4 V | 6 | ||
| LOW-level output voltage | VOL | 0.45 | V | VI = VIL; IO = 8 mA; VCCO = 1.65 V | 6 | ||
| LOW-level output voltage | VOL | 0.55 | V | VI = VIL; IO = 24 mA; VCCO = 3.0 V | 6 | ||
| input leakage current | II | -10 | 10 | μA | DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V | 6 | |
| OFF-state output current | IOZ | -10 | 10 | μA | A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V | 7 | |
| power-off leakage current | IOFF | -10 | 10 | μA | A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V | 7 | |
| supply current A plus B port | ICC | 16 | μA | A plus B port; IO = 0 A; VI = 0 V or VCCI; VCC(A), VCC(B) = 1.2 V to 5.5 V | 7 | ||
| supply current A plus B port | ICC | 4 | μA | A plus B port; IO = 0 A; VI = 0 V or VCCI; VCC(A), VCC(B) = 1.65 V to 5.5 V | 7 | ||
| supply current A port | ICC | 8 | μA | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A), VCC(B) = 1.2 V to 5.5 V | 7 | ||
| supply current A port | ICC | 3 | μA | A port; VI = 0 V or VCCI; IO = 0 A; VCC(A), VCC(B) = 1.65 V to 5.5 V | 7 | ||
| supply current B port | ICC | 8 | μA | B port; VI = 0 V or VCCI; IO = 0 A; VCC(A), VCC(B) = 1.2 V to 5.5 V | 7 | ||
| supply current B port | ICC | 3 | μA | B port; VI = 0 V or VCCI; IO = 0 A; VCC(A), VCC(B) = 1.65 V to 5.5 V | 7 | ||
| additional supply current | ΔICC | 75 | μA | A port at VCC(A) - 0.6 V; DIR at VCC(A); B port open; VCC(A), VCC(B) = 3.0 V to 5.5 V; non bus hold parts only | 8 | ||
| propagation delay LOW to HIGH A to B | tPLH | 1.1 | 6.9 | ns | Table 13; VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.3 V ±0.3 V; -40 °C to +125 °C | 12 | |
| propagation delay HIGH to LOW A to B | tPHL | 1.1 | 6 | ns | Table 13; VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.3 V ±0.3 V; -40 °C to +125 °C | 12 | |
| propagation delay HIGH to OFF-state DIR to B | tPHZ | 2.5 | 10.3 | ns | Table 13; VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.3 V ±0.3 V; -40 °C to +125 °C | 12 | |
| propagation delay LOW to OFF-state DIR to A | tPLZ | 1.5 | 6.4 | ns | Table 13; VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.3 V ±0.3 V; -40 °C to +125 °C | 12 | |
| propagation delay OFF-state to HIGH DIR to A | tPZH | 18.1 | ns | Table 13; VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.3 V ±0.3 V; -40 °C to +125 °C; calculated value | 12 | ||
| propagation delay OFF-state to LOW DIR to A | tPZL | 18 | ns | Table 13; VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.3 V ±0.3 V; -40 °C to +125 °C; calculated value | 12 |
CAD (KiCad official)
- Symbol:
74LVC1T45GM - Footprint:
Package_SON:Texas_USON-6_1x1.45mm_P0.5mm_SMD - 3D model: XSON-6(1x1.5) (KiCad packages3D, STEP)
- 3D model files:
74lvc1t45gm-etched.step/74lvc1t45gm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lvc1t45gm.step/74lvc1t45gm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (30 pp, sha256
2edba4df07cea429, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).