component

74LVC1GU04GW

Public Made by Adom

by adom

Nexperia Inverters, SOT-353. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs 74lvc1gu04gw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers 74lvc1gu04gw: viewers · Ray 2mo ago
74lvc1gu04gw-etched.fit.json 74lvc1gu04gw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74lvc1gu04gw-etched.glb 74lvc1gu04gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray 13d ago
74lvc1gu04gw-etched.step 74lvc1gu04gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray 13d ago
74lvc1gu04gw.glb Publish 0.1.0 · Ray 2mo ago
74lvc1gu04gw.kicad_mod Publish 0.1.0 · Ray 2mo ago
74lvc1gu04gw.kicad_sym Publish 0.1.0 · Ray 2mo ago
74lvc1gu04gw.lbr Publish 0.1.0 · Ray 2mo ago
74lvc1gu04gw.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.1.0 · Ray 2mo ago
page.json 74lvc1gu04gw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray 13d ago
README.md 74lvc1gu04gw: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74LVC1GU04GW

Nexperia · Inverters · SOT-353

74LVC1GU04GW from Nexperia, in a SOT-353. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 n.c. unconnected Not connected. No internal bond; leave floating or tie to GND/VCC per board convention.
2 A input Data input to the unbuffered inverter. Overvoltage-tolerant to 5.5 V regardless of V_CC. V_IH ≥ 0.75×V_CC (Tamb ≤ 85 °C) or 0.8×V_CC (extended range); V_IL ≤ 0.25×V_CC or 0.2×V_CC respectively.
3 GND power_in Ground reference (0 V). Sinks up to 100 mA absolute maximum I_GND.
4 Y output Data output; logical inverse of input A (L→H, H→L). Push-pull CMOS drive, ±24 mA at V_CC = 3.0 V (up to ±32 mA at V_CC = 4.5 V).
5 VCC power_in Positive supply voltage, 1.65 V to 5.5 V recommended (absolute max 6.5 V). Bypass locally with a ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-353
Category Logic
Pins 5

Ordering variants

  • 74LVC1GU04GW
  • 74LVC1GU04GWGV
  • 74LVC1GU04GWGM
  • 74LVC1GU04GWGN
  • 74LVC1GU04GWGS
  • 74LVC1GU04GWGX

CAD (KiCad official)

  • Symbol: 74LVC1GU04GW
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SOT-353 (KiCad packages3D, STEP)
  • 3D model files: 74lvc1gu04gw-etched.step / 74lvc1gu04gw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc1gu04gw.step / 74lvc1gu04gw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 5c76ef605a399d41, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF